XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 87

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS022-4 (v2.5) March 14, 2003
Virtex-E Pin Definitions
DS022-4 (v2.5) March 14, 2003
Production Product Specification
GCK0, GCK1,
GCK2, GCK3
BUSY/DOUT
M0, M1, M2
PROGRAM
DXN, DXP
TMS, TCK
Pin Name
TDI, TDO,
© 2000-2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
D0/DIN,
D1, D2,
D3, D4,
D5, D6,
WRITE
V
DONE
CCLK
V
V
GND
INIT
CCINT
CS
D7
CCO
REF
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Dedicated Pin
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
R
(Open-drain)
Bidirectional
Bidirectional
Direction
Input or
Input or
Output
Output
Output
Mixed
Input
Input
Input
Input
Input
Input
Input
Input
Input
N/A
0
0
In SelectMAP mode, the active-low Chip Select signal. The pin
Power-supply pins for the internal core logic.
www.xilinx.com
Clock input pins that connect to Global Clock Buffers.
Mode pins are used to specify the configuration mode.
The configuration Clock I/O pin: it is an input for SelectMAP and
slave-serial modes, and output in master-serial mode. After
configuration, it is input only, logic level = Don’t Care.
Initiates a configuration sequence when asserted Low.
Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output can be open drain.
When Low, indicates that the configuration memory is being cleared.
The pin becomes a user I/O after configuration.
In SelectMAP mode, BUSY controls the rate at which configuration
data is loaded. The pin becomes a user I/O after configuration unless
the SelectMAP port is retained.
In bit-serial modes, DOUT provides preamble and configuration data
to downstream devices in a daisy-chain. The pin becomes a user I/O
after configuration.
In SelectMAP mode, D0-7 are configuration data pins. These pins
become user I/Os after configuration unless the SelectMAP port is
retained.
In bit-serial modes, DIN is the single data input. This pin becomes a
user I/O after configuration.
In SelectMAP mode, the active-low Write Enable signal. The pin
becomes a user I/O after configuration unless the SelectMAP port is
retained.
becomes a user I/O after configuration unless the SelectMAP port is
retained.
Boundary-scan Test-Access-Port pins, as defined in IEEE1149.1.
Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)
Power-supply pins for the output drivers (subject to banking rules)
Input threshold voltage pins. Become user I/Os when an external
threshold voltage is not needed (subject to banking rules).
Ground
1-800-255-7778
0
Virtex™-E 1.8 V
Field Programmable Gate Arrays
Production Product Specification
Description
Module 4 of 4
1