XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 89

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Low Voltage Differential Signals
The Virtex-E family incorporates low-voltage signalling
(LVDS and LVPECL). Two pins are utilized for these signals
to be connected to a Virtex-E device. These are known as
differential pin pairs. Each differential pin pair has a Positive
(P) and a Negative (N) pin. These pairs are labeled in the
following manner.
where
I/O pins for differential signals can either be synchronous or
asynchronous, input or output. The pin pairs can be used for
synchronous input and output signals as well as asynchro-
nous input signals. However, only some of the low-voltage
pairs can be used for asynchronous output signals.
DIfferential signals require the pins of a pair to switch almost
simultaneously. If the signals driving the pins are from IOB
flip-flops, they are synchronous. If the signals driving the
pins are from internal logic, they are asynchronous.
defines the names and function of the different types of
low-voltage pin pairs in the Virtex-E family.
Virtex-E Package Pinouts
The Virtex-E family of FPGAs is available in 12 popular
packages, including chip-scale, plastic and high heat-dissi-
pation quad flat packs, and ball grid and fine-pitch ball grid
arrays. Family members have footprint compatibility across
devices provided in the same package. The pinout tables in
DS022-4 (v2.5) March 14, 2003
Production Product Specification
IO_L#[P/N]
L = LVDS or LVPECL pin
# = Pin Pair Number
P = Positive
N = Negative
R
Table 2
www.xilinx.com
1-800-255-7778
Table 2: LVDS Pin Pairs
this section indicate function, pin, and bank information for
each package/device combination. Following each pinout
table is an additional table summarizing information specific
to differential pin pairs for all devices provided in that pack-
age.
IO_L#[P/N]
Example: IO_L22N
IO_L#[P/N]_Y
Example: IO_L22N_Y
IO_L#[P/N]_YY
Example: O_L22N_YY
IO_LVDS_DLL_L#[P/N]
Example:
IO_LVDS_DLL_L16N
Virtex™-E 1.8 V Field Programmable Gate Arrays
Pin Name
Represents a general IO or a
synchronous input/output
differential signal. When used
as a differential signal, N
means Negative I/O and P
means Positive I/O.
Represents a general IO or a
synchronous input/output
differential signal, or a
part-dependent asynchronous
output differential signal.
Represents a general IO or a
synchronous input/output
differential signal, or an
asynchronous output
differential signal.
Represents a general IO or a
synchronous input/output
differential signal, a differential
clock input signal, or a DLL
input. When used as a
differential clock input, this pin
is paired with the adjacent
GCK pin. The GCK pin is
always the positive input in the
differential clock input
configuration.
Description
Module 4 of 4
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