XCV1600E-6BG560I Xilinx Inc, XCV1600E-6BG560I Datasheet - Page 9

• Manufacturer Part Number: XCV1600E-6BG560I
• Description: IC FPGA 1.8V I-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1600E-6BG560I

• Number Of Logic Elements/cells: 34992
• Number Of Labs/clbs: 7776
• Total Ram Bits: 589824
• Number Of I /o: 404
• Number Of Gates: 2188742
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in
multiple V
same voltage. This voltage is determined by the output
standards in use.
Within a bank, output standards can be mixed only if they
use the same V
Table
their open-drain outputs do not depend on V
Table 2: Compatible Output Standards
Some input standards require a user-supplied threshold
voltage, V
matically configured as inputs for the V
imately one in six of the I/O pins in the bank assume this
role.
The V
and consequently only one V
each bank. All V
nected to the external voltage source for correct operation.
Within a bank, inputs that require V
those that do not. However, only one V
used within a bank.
DS022-2 (v2.8) January 16, 2006
Production Product Specification
V
3.3 V
2.5 V
1.8 V
1.5 V
CCO
2. GTL and GTL+ appear under all voltages because
REF
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
CCO
REF
pins within a bank are interconnected internally
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,
R
. In this case, certain user-I/O pins are auto-
Figure 3: Virtex-E I/O Banks
HSTL I, HSTL III, HSTL IV, GTL, GTL+
pins, all of which must be connected to the
REF
CCO
Bank 0
Bank 5
pins in the bank, however, must be con-
. Compatible standards are shown in
LVCMOS18, GTL, GTL+
Compatible Standards
GCLK3 GCLK2
GCLK1 GCLK0
VirtexE
Device
GTL+, LVPECL
BLVDS, LVDS
REF
voltage can be used within
Bank 1
Bank 4
Figure
REF
ds022_03_121799
REF
REF
can be mixed with
3. Each bank has
voltage. Approx-
voltage can be
CCO
.
www.xilinx.com
In
LVCMOS18, PCI33_3, PCI66_3 standards are supplied by
V
and output buffers that have the same V
together.
The V
pin-out tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Within a given package, the number of V
can vary depending on the size of device. In larger devices,
more I/O pins convert to V
a super set of the V
possible to design a PCB that permits migration to a larger
device if necessary. All the V
anticipated must be connected to the V
used for I/O.
In smaller devices, some V
do not connect within the package. These unconnected pins
can be left unconnected externally, or can be connected to
the V
necessary.
Configurable Logic Blocks
The basic building block of the Virtex-E CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex-E CLB contains four LCs,
organized in two similar slices, as shown in
Figure 5
In addition to the four basic LCs, the Virtex-E CLB contains
logic that combines function generators to provide functions
of five or six inputs. Consequently, when estimating the
number of system gates provided by a given device, each
CLB counts as 4.5 LCs.
Look-Up Tables
Virtex-E function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be com-
bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
or a 16 x 1-bit dual-port synchronous RAM.
The Virtex-E LUT can also provide a 16-bit shift register that
is ideal for capturing high-speed or burst-mode data. This
mode can also be used to store data in applications such as
Digital Signal Processing.
CCO
Virtex-E,
CCO
CCO
rather than V
Virtex™-E 1.8 V Field Programmable Gate Arrays
shows a more detailed view of a single slice.
and V
voltage to permit migration to a larger device if
input
REF
CCINT
REF
pins for each bank appear in the device
buffers
pins used for smaller devices, it is
. For these standards, only input
REF
CCO
REF
pins. Since these are always
with
pins used in larger devices
pins for the largest device
LVTTL,
REF
REF
CCO
voltage, and not
and V
can be mixed
Module 2 of 4
LVCMOS2,
Figure
CCO
pins
4.
3