CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet - Page 10

• Manufacturer Part Number: CY7C68013A-128AXI
• Description: IC MCU USB PERIPH HI SPD 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-128AXI

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1943; CY7C68013A-128AXI

3.12 Endpoint RAM
3.12.1 Size
■
■
3.12.2 Organization
■
■
■
■
■
■
Document #: 38-08032 Rev. *M
3× 64 bytes
8 × 512 bytes
EP0
Bidirectional endpoint zero, 64 byte buffer
EP1IN, EP1OUT
64 byte buffers, bulk or interrupt
EP2, 4, 6, 8
Eight 512 byte buffers, bulk, interrupt, or isochronous. EP4 and
EP8 can be double buffered; EP2 and 6 can be either double,
triple, or quad buffered. For high speed endpoint configuration
options, see
Figure
EP0 IN&OUT
(Endpoints 0 and 1)
(Endpoints 2, 4, 6, 8)
EP1 OUT
5.
EP1 IN
EP8
EP2
EP4
EP6
512
512
512
512
512
512
512
512
1
64
64
64
EP4
EP6
EP2
512
512
512
512
512
512
512
512
64
64
64
2
EP2
EP4
EP6
1024
1024
512
512
512
512
64
64
64
3
Figure 5. Endpoint Configuration
EP2
EP8
EP6
512
512
512
512
512
512
512
512
64
64
64
4
EP2
EP6
512
512
512
512
512
512
512
512
64
64
64
5
EP2
EP6
1024
1024
3.12.3 Setup Data Buffer
A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data
from a CONTROL transfer.
3.12.4 Endpoint Configurations (High Speed Mode)
Endpoints 0 and 1 are the same for every configuration. Endpoint
0 is the only CONTROL endpoint, and endpoint 1 can be either
BULK or INTERRUPT.
The endpoint buffers can be configured in any 1 of the 12 config-
urations shown in the vertical columns. When operating in the full
speed BULK mode only the first 64 bytes of each buffer are used.
For example, in high speed, the max packet size is 512 bytes but
in full speed it is 64 bytes. Even though a buffer is configured to
a 512 byte buffer, in full speed only the first 64 bytes are used.
The unused endpoint buffer space is not available for other
operations. An example endpoint configuration is the EP2–1024
double buffered; EP6–512 quad buffered (column 8).
512
512
512
512
64
64
64
6
EP2
EP6
EP8
1024
1024
512
512
512
64
64
64
512
7
EP2
1024
1024
EP6
512
512
512
64
64
64
512
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
8
EP2
EP6
1024
1024
1024
1024
64
64
64
9
EP2
EP6
EP8
512
512
512
512
512
512
512
512
64
64
64
10
EP2 EP2
EP8
1024
1024
1024
1024
64
64
64
512
512
11
Page 10 of 62
1024
1024
1024
1024
12
64
64
64
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