CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet - Page 29

• Manufacturer Part Number: CY7C68013A-128AXI
• Description: IC MCU USB PERIPH HI SPD 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-128AXI

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1943; CY7C68013A-128AXI

5. Register Summary
FX2LP register bit definitions are described in the FX2LP TRM in greater detail.
Table 12. FX2LP Register Summary
Document #: 38-08032 Rev. *M
Hex
E400 128 WAVEDATA
E480 128 reserved
E50D
E600 1
E601 1
E602 1
E603 1
E604 1
E605 1
E606 1
E607 1
E608 1
E609 1
E60A 1
E60B 1
E60C 1
E610 1
E611 1
E612 1
E613 1
E614 1
E615 1
E618 1
E619 1
E61A 1
E61B 1
E61C 4
E620 1
E621 1
E622 1
E623 1
E624 1
E625 1
E626 1
E627 1
E628 1
E629 1
E62A 1
Note
11. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
Size Name
3
2
GPIF Waveform Memories
GENERAL CONFIGURATION
GPCR2
CPUCS
IFCONFIG
PINFLAGSAB
PINFLAGSCD
FIFORESET
BREAKPT
BPADDRH
BPADDRL
UART230
FIFOPINPOLAR
REVID
REVCTL
UDMA
GPIFHOLDAMOUNT MSTB Hold Time
reserved
ENDPOINT CONFIGURATION
EP1OUTCFG
EP1INCFG
EP2CFG
EP4CFG
EP6CFG
EP8CFG
reserved
EP2FIFOCFG
EP4FIFOCFG
EP6FIFOCFG
EP8FIFOCFG
reserved
EP2AUTOINLENH
EP2AUTOINLENL
EP4AUTOINLENH
EP4AUTOINLENL
EP6AUTOINLENH
EP6AUTOINLENL
EP8AUTOINLENH
EP8AUTOINLENL
ECCCFG
ECCRESET
ECC1B0
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11]
[11
[11]
[11]
[11]
Description
GPIF Waveform
Descriptor 0, 1, 2, 3 data
General Purpose Configu-
ration Register 2
CPU Control & Status
Interface Configuration
(Ports, GPIF, slave FIFOs)
Slave FIFO FLAGA and
FLAGB Pin Configuration
Slave FIFO FLAGC and
FLAGD Pin Configuration
Restore FIFOS to default
state
Breakpoint Control
Breakpoint Address H
Breakpoint Address L
230 Kbaud internally
generated ref. clock
Slave FIFO Interface pins
polarity
Chip Revision
Chip Revision Control
(for UDMA)
Endpoint 1-OUT
Configuration
Endpoint 1-IN
Configuration
Endpoint 2 Configuration VALID
Endpoint 4 Configuration VALID
Endpoint 6 Configuration VALID
Endpoint 8 Configuration VALID
Endpoint 2 / slave FIFO
configuration
Endpoint 4 / slave FIFO
configuration
Endpoint 6 / slave FIFO
configuration
Endpoint 8 / slave FIFO
configuration
Endpoint 2 AUTOIN
Packet Length H
Endpoint 2 AUTOIN
Packet Length L
Endpoint 4 AUTOIN
Packet Length H
Endpoint 4 AUTOIN
Packet Length L
Endpoint 6 AUTOIN
Packet Length H
Endpoint 6 AUTOIN
Packet Length L
Endpoint 8 AUTOIN
Packet Length H
Endpoint 8 AUTOIN
Packet Length L
ECC Configuration
ECC Reset
ECC1 Byte 0 Address
b7
D7
reserved
0
IFCLKSRC
FLAGB3
FLAGD3
NAKALL
0
A15
A7
0
0
rv7
0
0
VALID
VALID
0
0
0
0
0
PL7
0
PL7
0
PL7
0
PL7
0
x
LINE15
b6
D6
reserved
0
3048MHZ
FLAGB2
FLAGD2
0
0
A14
A6
0
0
rv6
0
0
0
0
DIR
DIR
DIR
DIR
INFM1
INFM1
INFM1
INFM1
0
PL6
0
PL6
0
PL6
0
PL6
0
x
LINE14
b5
D5
reserved
PORTCSTB CLKSPD1
IFCLKOE
FLAGB1
FLAGD1
0
0
A13
A5
0
PKTEND
rv5
0
0
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
OEP1
OEP1
OEP1
OEP1
0
PL5
0
PL5
0
PL5
0
PL5
0
x
LINE13
b4
D4
FULL_SPEE
D_ONLY
IFCLKPOL
FLAGB0
FLAGD0
0
0
A12
A4
0
SLOE
rv4
0
0
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
AUTOOUT
AUTOOUT
AUTOOUT
AUTOOUT
0
PL4
0
PL4
0
PL4
0
PL4
0
x
LINE12
b3
D3
reserved
CLKSPD0
ASYNC
FLAGA3
FLAGC3
EP3
BREAK
A11
A3
0
SLRD
rv3
0
0
0
0
SIZE
0
SIZE
0
AUTOIN
AUTOIN
AUTOIN
AUTOIN
0
PL3
0
PL3
0
PL3
0
PL3
0
x
LINE11
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
b2
D2
reserved
CLKINV
GSTATE
FLAGA2
FLAGC2
EP2
BPPULSE
A10
A2
0
SLWR
rv2
0
0
0
0
0
0
0
0
ZEROLENIN 0
ZEROLENIN 0
ZEROLENIN 0
ZEROLENIN 0
PL10
PL2
0
PL2
PL10
PL2
0
PL2
0
x
LINE10
b1
D1
reserved
CLKOE
IFCFG1
FLAGA1
FLAGC1
EP1
BPEN
A9
A1
230UART1
EF
rv1
dyn_out
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
0
0
BUF1
0
BUF1
0
PL9
PL1
PL9
PL1
PL9
PL1
PL9
PL1
0
x
LINE9
b0
D0
reserved
8051RES
IFCFG0
FLAGA0
FLAGC0
EP0
0
A8
A0
230UART0
FF
rv0
enh_pkt
0
0
BUF0
0
BUF0
0
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
PL8
PL0
PL8
PL0
PL8
PL0
PL8
PL0
ECCM
x
LINE8
Page 29 of 62
Default
xxxxxxxx RW
00000000 R
00000010 rrbbbbbr
10000000 RW
00000000 RW
00000000 RW
xxxxxxxx W
00000000 rrrrbbbr
xxxxxxxx RW
xxxxxxxx RW
00000000 rrrrrrbb
00000000 rrbbbbbb
RevA
00000001
00000000 rrrrrrbb
10100000 brbbrrrr
10100000 brbbrrrr
10100010 bbbbbrbb
10100000 bbbbrrrr
11100010 bbbbbrbb
11100000 bbbbrrrr
00000010 rrrrrbbb
00000000 RW
00000010 rrrrrrbb
00000000 RW
00000010 rrrrrbbb
00000000 RW
00000010 rrrrrrbb
00000000 RW
00000000 rrrrrrrb
00000000 W
00000000 R
Access
R
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