CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet - Page 52

• Manufacturer Part Number: CY7C68013A-128AXI
• Description: IC MCU USB PERIPH HI SPD 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-128AXI

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1943; CY7C68013A-128AXI

10.17.3 Sequence Diagram of a Single and Burst Asynchronous Read
Figure 32
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
■
■
■
Document #: 38-08032 Rev. *M
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of t
t
SLRD is asserted (The SLCS and SLRD signals must both be
asserted to start a valid read condition.)
RDpwh
FIFOADR
FLAGS
FIFO POINTER
FIFO DATA BUS Not Driven
DATA
SLRD
SLCS
SLOE
. If SLCS is used then, SLCS must be asserted before
shows the timing relationship of the SLAVE FIFO
RDpwl
t=0
t=1
N
Driven
Data (X)
and minimum de-active pulse width of
t
Figure 32. Slave FIFO Asynchronous Read Sequence and Timing Diagram
SFA
t
OEon
SLOE
t=2
Figure 33. Slave FIFO Asynchronous Read Sequence of Events Diagram
t
RDpwl
Driven: X
t
XFD
t=3
N
N
t=4
t
RDpwh
t
FAH
SLRD
t
OEoff
t
XFLG
N
N
SLRD
T=0
N+1
T=1
N
SLOE
t
t
SFA
OEon
N
T=2
Not Driven
t
N+1
RDpwl
t
XFD
T=3
SLOE
■
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After SLRD is
asserted, the data from the FIFO is driven on the data bus (SLOE
must also be asserted) and then the FIFO pointer is incre-
mented.
The data that is driven, after asserting SLRD, is the updated
data from the FIFO. This data is valid after a propagation delay
of t
is the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (SLRD is asserted), SLOE
must be in an asserted state. SLRD and SLOE can also be tied
together.
t
N+1
RDpwh
XFD
N+1
N
T=4
SLRD
from the activating edge of SLRD. In
t
RDpwl
t
XFD
N+1
T=5
N+1
SLRD
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
t
N+2
RDpwh
N+2
T=6
N+1
SLRD
t
RDpwl
t
XFD
N+3
N+2
N+2
T=7
t
t
RDpwh
FAH
SLRD
t
[20]
OEoff
t
XFLG
N+3
N+2
Page 52 of 62
Figure
SLOE
Not Driven
32, data N
N+3
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