CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet - Page 2

• Manufacturer Part Number: CY7C68013A-128AXI
• Description: IC MCU USB PERIPH HI SPD 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-128AXI

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1943; CY7C68013A-128AXI

1.1 Features (CY7C68013A/14A only)
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1.2 Features (CY7C68015A/16A only)
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Cypress’s EZ-USB FX2LP™ (CY7C68013A/14A) is a low power
version of the EZ-USB FX2™ (CY7C68013), which is a highly
integrated, low power USB 2.0 microcontroller. By integrating the
USB 2.0 transceiver, serial interface engine (SIE), enhanced
8051 microcontroller, and a programmable peripheral interface
in a single chip,
Document #: 38-08032 Rev. *M
Logic Block Diagram
CY7C68014A: Ideal for Battery Powered Applications
❐
CY7C68013A: Ideal for Non-battery Powered Applications
❐
Available in Five Pb-free Packages with Up to 40 GPIOs
❐
CY7C68016A: Ideal for Battery Powered Applications
❐
CY7C68015A: Ideal for Non-battery Powered Applications
❐
Available in Pb-free 56-pin QFN Package (26 GPIOs)
❐
Suspend current: 100 μA (typ)
Suspend current: 300 μA (typ)
128-pin TQFP (40 GPIOs), 100-pin TQFP (40 GPIOs), 56-pin
QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VF-
BGA (24 GPIOs)
Suspend current: 100 μA (typ)
Suspend current: 300 μA (typ)
Two more GPIOs than CY7C68013A/14A enabling additional
features in same footprint
full speed and
Integrated
high speed
XCVR
D+
D–
FX2LP
VCC
1.5k
connected for
full speed
Enhanced USB core
Simplifies 8051 code
XCVR
USB
24 MHz
Ext. XTAL
2.0
x20
PLL
/0.5
/1.0
/2.0
1.1/2.0
Smart
Engine
USB
CY
High performance micro
using standard tools
with lower-power options
four clocks/cycle
Easy firmware changes
12/24/48 MHz,
8051 Core
“Soft Configuration”
16 KB
RAM
Cypress has created a cost effective solution that provides
superior time-to-market advantages with low power to enable
bus powered applications.
The ingenious architecture of FX2LP results in data transfer
rates of over 53 Mbytes per second, the maximum allowable
USB 2.0 bandwidth, while still using a low cost 8051 microcon-
troller in a package as small as a 56 VFBGA (5 mm x 5 mm).
Because it incorporates the USB 2.0 transceiver, the FX2LP is
more economical, providing a smaller footprint solution than
USB 2.0 SIE or external transceiver implementations. With
EZ-USB FX2LP, the Cypress Smart SIE handles most of the
USB 1.1 and 2.0 protocol in hardware, freeing the embedded
microcontroller for application specific functions and decreasing
development time to ensure USB compatibility.
The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and
glueless interface to popular interfaces such as ATA, UTOPIA,
EPP, PCMCIA, and most DSP/processors.
The FX2LP draws less current than the FX2 (CY7C68013), has
double the on-chip code/data RAM, and is fit, form and function
compatible with the 56, 100, and 128 pin FX2.
Five packages are defined for the family: 56VFBGA, 56 SSOP,
56 QFN, 100 TQFP, and 128 TQFP.
ECC
FIFO and endpoint memory
(master or slave operation)
Additional I/Os (24)
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
GPIF
FIFO
4 kB
Master
I
2
C
ADDR (9)
RDY (6)
CTL (6)
8/16
including two USARTS
standards such as
ATAPI, EPP, etc.
programmable I/F
General
to ASIC/DSP or bus
Up to 96 MBytes/s
Abundant I/O
burst rate
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