CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet - Page 21

• Manufacturer Part Number: CY7C68013A-128AXI
• Description: IC MCU USB PERIPH HI SPD 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-128AXI

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1943; CY7C68013A-128AXI

4.1 CY7C68013A/15A Pin Descriptions
The FX2LP Pin Descriptions follows.
Table 11. FX2LP Pin Descriptions
Document #: 38-08032 Rev. *M
TQFP
Note
10. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in
128
120
126
127
128
117
118
119
17
13
20
19
18
94
95
96
97
21
22
23
24
25
59
60
61
62
63
86
87
88
39
10
standby. Note also that no pins should be driven while the device is powered down.
TQFP
100
16
12
19
18
17
9
SSOP
56
10
14
13
17
16
15
QFN
56
10
3
7
6
9
8
56 VF-
BGA
2D
1D
1E
2E
2F
1F
[10]
AVCC
AVCC
AGND
AGND
DMINUS
DPLUS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
PSEN#
Name
Ground
Ground
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Default
N/A
N/A
N/A
N/A
H
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
Analog VCC. Connect this pin to 3.3V power source.
This signal provides power to the analog section of the
chip.
Analog VCC. Connect this pin to 3.3V power source.
This signal provides power to the analog section of the
chip.
Analog Ground. Connect to ground with as short a path
as possible.
Analog Ground. Connect to ground with as short a path
as possible.
USB D– Signal. Connect to the USB D– signal.
USB D+ Signal. Connect to the USB D+ signal.
8051 Address Bus. This bus is driven at all times.
When the 8051 is addressing internal RAM it reflects
the internal address.
8051 Data Bus. This bidirectional bus is high
impedance when inactive, input for bus reads, and
output for bus writes. The data bus is used for external
8051 program and data memory. The data bus is active
only for external bus accesses, and is driven LOW in
suspend.
Program Store Enable. This active-LOW signal
indicates an 8051 code fetch from external memory. It
is active for program memory fetches from
0x4000–0xFFFF when the EA pin is LOW, or from
0x0000–0xFFFF when the EA pin is HIGH.
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Description
Page 21 of 62
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