CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet - Page 23

• Manufacturer Part Number: CY7C68013A-128AXI
• Description: IC MCU USB PERIPH HI SPD 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-128AXI

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1943; CY7C68013A-128AXI

Table 11. FX2LP Pin Descriptions (continued)
Document #: 38-08032 Rev. *M
TQFP
Port B
128
85
89
90
91
92
44
45
46
47
54
TQFP
100
70
71
72
73
74
34
35
36
37
44
SSOP
56
43
44
45
46
47
25
26
27
28
29
QFN
56
36
37
38
39
40
18
19
20
21
22
56 VF-
BGA
4G
8C
7C
6C
3H
4H
5H
7F
6F
4F
PA3 or
WU2
PA4 or
FIFOADR0
PA5 or
FIFOADR1
PA6 or
PKTEND
PA7 or
FLAGD or
SLCS#
PB0 or
FD[0]
PB1 or
FD[1]
PB2 or
FD[2]
PB3 or
FD[3]
PB4 or
FD[4]
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Default
(PB0)
(PB1)
(PB2)
(PB3)
(PB4)
(PA3)
(PA4)
(PA5)
(PA6)
(PA7)
I
I
I
I
I
I
I
I
I
I
Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled
by WU2EN bit (WAKEUP.1) and polarity set by
WU2POL (WAKEUP.4). If the 8051 is in suspend and
WU2EN = 1, a transition on this pin starts up the oscil-
lator and interrupts the 8051 to enable it to exit the
suspend mode. Asserting this pin inhibits the chip from
suspending, if WU2EN = 1.
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave
FIFOs connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave
FIFOs connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by the
IFCONFIG[1:0] bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet
data to the endpoint and whose polarity is program-
mable via FIFOPINPOLAR.5.
Multiplexed pin whose function is selected by the
IFCONFIG[1:0] and PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status
flag signal.
SLCS# gates all other slave FIFO enable/strobes
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
Multiplexed pin whose function is selected by the
following bits: IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
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