CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet - Page 27

• Manufacturer Part Number: CY7C68013A-128AXI
• Description: IC MCU USB PERIPH HI SPD 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-128AXI

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1943; CY7C68013A-128AXI

Table 11. FX2LP Pin Descriptions (continued)
Document #: 38-08032 Rev. *M
TQFP
128
106
70
71
66
67
98
32
28
31
30
29
53
52
51
TQFP
100
55
56
51
52
76
26
22
84
25
24
23
43
42
41
SSOP
56
37
38
20
QFN
56
30
31
13
56 VF-
BGA
7G
2G
8H
CTL1 or
FLAGB
CTL2 or
FLAGC
CTL3
CTL4
CTL5
IFCLK on
CY7C68013A
and
CY7C68014A
------------------
PE0 on
CY7C68015A
and
CY7C68016A
INT4
INT5#
T2
T1
T0
RXD1
TXD1
RXD0
Name
-----------
Output
Output
Output
Type
I/O/Z
I/O/Z
Input
Input
Input
Input
Input
Input
Input
O/Z
O/Z
O/Z
Default
----------
N/A
N/A
N/A
N/A
N/A
N/A
N/A
H
H
H
H
H
H
Z
I
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status
flag signal.
Defaults to FULL for the FIFO selected by the
FIFOADR[1:0] pins.
Multiplexed pin whose function is selected by the
following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status
flag signal.
Defaults to EMPTY for the FIFO selected by the
FIFOADR[1:0] pins.
CTL3 is a GPIF control output.
CTL4 is a GPIF control output.
CTL5 is a GPIF control output.
Interface Clock, used for synchronously clocking data
into or out of the slave FIFOs. IFCLK also serves as a
timing reference for all slave FIFO control signals and
GPIF. When internal clocking is used (IFCONFIG.7 = 1)
the IFCLK pin can be configured to output 30/48 MHz
by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be
inverted, whether internally or externally sourced, by
setting the bit IFCONFIG.4 =1.
-----------------------------------------------------------------------
PE0 is a bidirectional I/O port pin.
INT4 is the 8051 INT4 interrupt request input signal. The
INT4 pin is edge-sensitive, active HIGH.
INT5# is the 8051 INT5 interrupt request input signal.
The INT5 pin is edge-sensitive, active LOW.
T2 is the active-HIGH T2 input signal to 8051 Timer2,
which provides the input to Timer2 when C/T2 = 1.
When C/T2 = 0, Timer2 does not use this pin.
T1 is the active-HIGH T1 signal for 8051 Timer1, which
provides the input to Timer1 when C/T1 is 1. When C/T1
is 0, Timer1 does not use this bit.
T0 is the active-HIGH T0 signal for 8051 Timer0, which
provides the input to Timer0 when C/T0 is 1. When C/T0
is 0, Timer0 does not use this bit.
RXD1is an active-HIGH input signal for 8051 UART1,
which provides data to the UART in all modes.
TXD1is an active-HIGH output pin from 8051 UART1,
which provides the output clock in sync mode, and the
output data in async mode.
RXD0 is the active-HIGH RXD0 input to 8051 UART0,
which provides data to the UART in all modes.
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Description
Page 27 of 62
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