CY7C68013A-128AXI Cypress Semiconductor Corp, CY7C68013A-128AXI Datasheet - Page 46

• Manufacturer Part Number: CY7C68013A-128AXI
• Description: IC MCU USB PERIPH HI SPD 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-128AXI

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3684
• Minimum Operating Temperature: - 40 C
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Program Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, USART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1943; CY7C68013A-128AXI

10.10 Slave FIFO Asynchronous Write
Table 25. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
10.11 Slave FIFO Synchronous Packet End Strobe
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Table 27. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
Document #: 38-08032 Rev. *M
t
t
t
t
t
t
t
t
t
t
t
t
t
WRpwl
WRpwh
SFD
FDH
XFD
IFCLK
SPE
PEH
XFLG
IFCLK
SPE
PEH
XFLG
Parameter
Parameter
Parameter
SLWR Pulse LOW
SLWR Pulse HIGH
SLWR to FIFO DATA Setup Time
FIFO DATA to SLWR Hold Time
SLWR to FLAGS Output Propagation Delay
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
Figure 22. Slave FIFO Synchronous Packet End Strobe Timing Diagram
SLWR/SLCS#
Figure 21. Slave FIFO Asynchronous Write Timing Diagram
PKTEND
FLAGS
DATA
FLAGS
SLWR
IFCLK
Description
Description
Description
t
WRpwl
t
SFD
t
XFD
t
FDH
t
SPE
t
WRpwh
t
t
PEH
XFLG
20.83
20.83
14.6
Min
Min
Min
8.6
2.5
50
70
10
10
0
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
[23]
[20]
Max
Max
Max
13.5
200
9.5
70
[20]
[21]
[21]
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Unit
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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