DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 11

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Table 4. Transceiver PCS Features
External Memory and General Purpose I/O
Stratix V devices offer high I/O bandwidth with up to seven 72-bit DDR3 memory interfaces running at
1066 MHz / 2133 Mbps and ubiquitous LVDS running at 1.4 Gbps. This translates to an aggregate
memory bandwidth of 1075 Gbps and LVDS bandwidth of 315 Gbps.
Significant architectural enhancements in the I/O blocks increase the overall external memory
performance (see Figure 6). First, all timing critical circuits in the DDR read-and-write paths are hardened
in the I/O block to enable timing closure at 1066 MHz. Second, each I/O block has a hard FIFO that
improves the resynchronization margin as the data is transferred from memory to the FPGA. The hard
FIFO also lowers PHY latency, resulting in higher random access performance. Third, the I/Os include
on-chip dynamic termination to reduce the number of external components and minimize reflections.
Altera Corporation
Custom 10G PHY
OTN 40 and 100
×1, ×4, ×8 PCIe
×1, ×4, ×8 PCIe
100GBASE-R
10G Ethernet
Custom PHY
40GBASE-R
Protocol
Interlaken
Ethernet
Ethernet
Gen 1/2
GPON
Gen 3
SRIO
CPRI
XAUI
GbE
0.6144 to 9.83
(10 +1) × 11.3
Data Rates
10 × 10.3125
3.125 to 4.25
(4 +1) × 11.3
1.25 and 2.5
4 × 10.3125
9.98 to 14.1
1.25 to 6.25
2.5 and 5.0
4.9 to 14.1
0.6 to 8.5
(Gbps)
10.3125
1.25
8.5
Phase compensation FIFO, byte
serializer, 8B/10B encoder, bit-slipper,
channel bonding
TX FIFO, gear box and bit-slipper
Same as custom PHY plus PIPE 2.0
interface to core logic
Phase compensation FIFO, encoder,
scrambler, gear box, and bit slip
TX FIFO, 64/66 encoder, scrambler, and
gear box
TX FIFO, frame generator, CRC-32
generator. scrambler, disparity generator,
and gear box
TX FIFO, 64/66 encoder, scrambler,
alignment marker insertion, gear box,
and block striper
TX FIFO, channel bonding, and byte
serializer
Same as custom PHY plus GbE state
machine
Same as custom PHY plus XAUI state
machine for bonding 4 channels
Same as custom PHY plus SRIO V2.1
compliant ×2 and ×4 channel bonding
Same as custom PHY plus TX
deterministic latency
Same as custom PHY
Transmit Data Path
Word aligner, de-skew FIFO, rate match
FIFO, 8B/10B decoder, byte deserializer,
and byte ordering
RX FIFO and gear box
Same as custom PHY plus PIPE 2.0
interface to core logic
Block synchronization, rate match FIFO,
decoder, de-scrambler, and phase
compensation FIFO
RX FIFO, 64/66 decoder, de-scrambler,
block synchronization, and gear box
RX FIFO, frame generator, CRC-32
checker, frame decoder, descrambler,
disparity checker, block synchronization,
and gear box
RX FIFO, 64/66 decoder, de-scrambler,
lane reorder, deskew, alignment marker
lock, block synchronization, gear box,
and destripper
RX FIFO, lane deskew, and byte de-
serializer
Same as custom PHY plus GbE state
machine
Same as custom PHY plus XAUI state
machine for re-aligning 4 channels
Same as custom PHY plus SRIO V2.1
compliant ×2 and ×4 deskew state
machine
Same as custom PHY plus RX
deterministic latency
Same as custom PHY
Stratix V Device Family User Guide Lite
Receiver Data Path
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