DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 12

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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Fourth, the on-package decoupling (OPD) capacitors suppress noise on the power lines, which reduce
noise coupling into the I/Os. Last, the memory banks are isolated to prevent core noise from coupling to
the output; thus reducing jitter and providing optimal signal integrity.
The external memory interface block also uses advanced calibration algorithms to compensate for PVT
(process, voltage and temperature) variations in the FPGA and external memory components. These
advanced algorithms ensure maximum bandwidth and robust timing margin across all conditions. Stratix
V devices also deliver a complete memory solution with High Performance Memory Controller II (HPMC
II) and UniPHY Megacores that simplify design for today’s advanced memory modules. Table 5 shows
external memory interface block performance.
Figure 7. Stratix V FPGA PHY Architecture (UniPHY) for Implementing Memory Subsystems Quickly and Easily
Table 5. External Memory Interface Performance
Adaptive Logic Module (ALM)
Stratix V devices use an improved adaptive logic module (ALM) to implement logic functions more
efficiently. The ALM shown in Figure 8 has eight inputs with a fracturable look-up table (LUT), two
dedicated embedded adders and four dedicated registers.
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Altera Corporation
RLDRAM III
RLDRAM II
Interface
QDR II+
QDR II
DDR3
DDR2
Performance
1066 MHz
533 MHz
400 MHz
667 MHz
800 MHz
667 MHz
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Stratix V Device Family User Guide Lite