DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 15

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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circuit domain and automatically biases core logic to meet performance and optimize power
consumption.
Additionally, Stratix V devices have a number of hard IP blocks that not only reduce logic resources but
also deliver substantial power savings compared to soft implementations. The list includes PCI Express
Gen 3/2/1, 10G/40G/100G Ethernet, Interlaken PCS, hard I/O FIFOs and transceivers. Hard IP blocks
consume up to 50% less power than equivalent soft implementations.
Stratix V transceivers are also designed for power efficiency. As a result, the transceiver channels
consume 50% less power than the previous generation Stratix IV FPGAs. The transceiver PMA consumes
90mW at 6.5 Gbps and 170 mW at 12.5 Gbps.
Lastly, Stratix V devices are built on TSMC high-performance, high-k metal gate (HKMG), 28-nm process
node. 28-nm silicon operates at a supply voltage of 0.85 V whereas 40-nm silicon operates at 0.90 V. The
50 mV lower supply voltage also reduces FPGA power consumption, translating to a 12% dynamic power
savings.
Figure 10. Stratix V FPGAs Deliver 30% Less Total Power, while Providing the Industry’s Highest Performance
Incremental Compilation
The Quartus II design software incremental compilation feature reduces compilation time by up to 70%
and preserves performance to ease timing closure. Incremental compilation supports top-down, bottom-
up, and team-based design flows. The incremental compilation feature facilitates modular hierarchical
and team-based design flows where different designers compile their respective sections of a design in
parallel. Furthermore, different designers or IP providers can develop and optimize different blocks of
the design independently, and then you can import these blocks into the top-level project. The
incremental compilation feature enables the partial reconfiguration flow of Stratix V devices.
Enhanced Configuration and Configuration via PCI Express
Stratix V device configuration is enhanced for ease-of-use, speed and cost. These devices support a new 4-
bit bus Active Serial mode (AS×4) and Configuration by Protocol (CvP), where ASx4 supports up to 400
Mbps data rate using small low cost quad interface Flash devices. This new mode is easy to use and offers
an ideal balance between cost and speed. Finally the Fast Passive Parallel (FPP) interface is enhanced to
support 8-, 16-, and 32-bit data widths to meet a wide range of performance and cost goals.
Stratix V FPGAs can now be configured through PCI Express CvP instead of an external flash or ROM.
CvP offers the fastest configuration rate and flexibility with the easy-to-use PCI Express hard IP block
interface. CvP meets the PCI Express 100 ms power-up to active time requirement. Stratix V devices and
the Quartus II software support partial reconfiguration through CvP, which reduces system downtime by
keeping the PCI Express link alive while the FPGA is reconfigured.
Altera Corporation
Stratix V Device Family User Guide Lite