DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet

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... Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.3 11.0 Stratix V Device Handbook Volume 1: Overview and Datasheet ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21 High-Speed I/O Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22 DQ Logic Block and Memory Output Clock Jitter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 2–26 OCT Calibration Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28 Duty Cycle Distortion (DCD) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–28 June 2011 Altera Corporation Contents Stratix V Device Handbook Volume 1: Overview and Datasheet ...

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... Programmable IOE Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29 Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–30 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33 Additional Information How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Stratix V Device Handbook Volume 1: Overview and Datasheet Contents June 2011 Altera Corporation ...

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... Chapter 1. Stratix V Device Family Overview Revised: Part Number: SV51001-1.8 Chapter 2. DC and Switching Characteristics for Stratix V Devices Revised: Part Number: SV53001-2.0 June 2011 Altera Corporation June 2011 May 2011 Stratix V Device Handbook Volume 1: Overview and Datasheet Chapter Revision Dates ...

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... Stratix V Device Handbook Volume 1: Overview and Datasheet Chapter Revision Dates June 2011 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Kbit (M20K) embedded memory blocks, variable precision DSP blocks, and fractional phase-locked loops (PLLs). All of these building blocks are interconnected by Altera’s superior multi-track routing architecture and comprehensive fabric clocking network. Also common to Stratix V devices is the new Embedded HardCopy Block, which is a customizable hard IP block that leverages Altera’ ...

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... High-performance core fabric ■ Enhanced ALM with four registers ■ Improved routing architecture reduces congestion and ■ improves compile times June 2011 Altera Corporation Embedded memory blocks ■ M20K: 20-Kbit with hard error correction code (ECC) ■ MLAB: 640-bit ■ Variable precision DSP blocks ■ ...

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... Migration between select Stratix V GT devices and Stratix V GX devices is available. For more information, refer to Table 1–5 on page Stratix V Device Handbook Features 5SGTC5 2,304 (3) 5SGTC5 600, 150, 4/32 Package Information Datasheet for Altera 1–9. Chapter 1: Stratix V Device Family Overview Stratix V Family Plan 5SGTC7 425 622 642 939 ...

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Table 1–2 lists the Stratix V GX device features. Table 1–2. Stratix V GX Device Features (Part Features 5SGXA3 Logic Elements (K) 200 Registers (K) 302 14.1-Gbps Transceivers PCIe hard IP Blocks 1 or ...

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Table 1–2. Stratix V GX Device Features (Part Features 5SGXA3 NF45-F1932 (5) — Notes to Table 1–2: (1) Packages are flipchip ball grid array (1.0-mm pitch). (2) LVDS counts are full duplex channels. Each full duplex channel ...

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Table 1–3 lists the Stratix V GS device features. Table 1–3. Stratix V GS Device Features Features 5SGSD2 Logic Elements (K) Registers (K) 14.1-Gbps transceivers PCIe hard IP blocks Fractional PLL M20K Memory Blocks M20K Memory (MBits) Variable Precision Multipliers ...

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... Chapter 1: Stratix V Device Family Overview Stratix V Family Plan 5SEEB 840 950 1,434 28 28 2,640 52 52 704 704 352 352 7 7 5SEEB 552, 138 696, 174 840, 210 June 2011 Altera Corporation ...

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Each row in Table 1–5 lists which devices allow migration. Table 1–5. Device Migration List Across All Stratix V Device Variants Package HH29-H780 H35-H1152 DF23-F484 EF29-F780 GF35/HF35-F1152 ( KF35-F1152 ...

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... Chapter 1: Stratix V Device Family Overview Table 1–6 lists the transceiver PMA features. (Note 1) Hard PCS Hard PCS Core Logic Hard PCS Fabric Hard PCS Hard PCS Low-Power Serial Transceivers Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA Transceiver PMA (2) June 2011 Altera Corporation ...

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... Custom 10G PHY 9.98 to 14.1 ×1, ×4, ×8 PCIe 2.5 and 5.0 Gen 1/2 June 2011 Altera Corporation Capability 10GBASE-R, 14.1 Gbps (Stratix V GX/GS devices), 12.5 Gbps (Stratix V GT devices) PCIe cable and eSATA applications 10G Form-factor Pluggable (XFP), Small Form-factor Pluggable (SFP+), Quad ...

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... Same as custom PHY plus GbE state machine Same as custom PHY plus XAUI state machine for re-aligning four channels Same as custom PHY plus SRIO V2.1-compliant ×2 and ×4 deskew state machine Same as Custom PHY plus RX deterministic latency Same as custom PHY June 2011 Altera Corporation ...

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... Table 1–8. External Memory Interface Performance Note to Table 1–8: (1) The specifications listed in this table are performance targets. For a current achievable performance, use the External Memory Interface Spec June 2011 Altera Corporation ® IP that simplify a design for today’s Table 1–8 lists external memory interface block (Note 1) ...

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... The Stratix V device core clock network is designed to support 717-MHz fabric operations and 1,066-MHz/1,600-Mbps external memory interfaces. The clock network architecture is based on Altera’s proven global, quadrant, and peripheral clock structure, which is supported by dedicated clock input pins and fractional clock synthesis PLLs. The Quartus II software identifies all unused sections of the clock network and powers them down, which reduces power consumption ...

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... Variable Precision DSP Block 18×18 1/2 of Variable Precision DSP Block 27×27 1 Variable Precision DSP Block 36×36 2 Variable Precision DSP Block June 2011 Altera Corporation Table 1–9. MLAB (640 Bits) 32×20 64×10 High precision fixed or single precision floating point Very high precision fixed point M20K (20,480 Bits) 512× ...

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... Stratix V Device Handbook Chapter 1: Stratix V Device Family Overview Variable Precision DSP Block Table 1–11 lists Expected Usage Resource optimized FFTs Accommodate bit growth through FFT stages Highest precision FFT stages Single precision floating point June 2011 Altera Corporation ...

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... CvP uses a much smaller amount of external memory (flash or ROM) because it only has to store the configuration file for the PCIe hard IP and periphery. Also, the 100 ms power-up to active time (for PCIe) is much June 2011 Altera Corporation 1–17 Stratix V Device Handbook ...

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... FPGA, saving board space and reducing power now, partial reconfiguration solutions have been time-intensive tasks that required you to know all of the intricate FPGA architecture details. Altera simplifies the partial reconfiguration process by building the capability on top of the proven incremental compilation design flow in its Quartus II design software. ...

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... Whether you plan for ASIC production and require the lowest-risk, lowest-cost path from specification to production or require a cost reduction path for your FPGA-based systems, Altera provides the optimal solution for power, performance, and device bandwidth. June 2011 Altera Corporation 1– ...

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Ordering Information This section describes ordering information for Stratix V GT, GX, GS, and E devices. Stratix V devices. Figure 1–2. Ordering Information for Stratix V Devices Embedded Family Variant Hardcopy Block Variant GT: 28 Gbps Transceivers ...

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... July 2010 1.2 May 2010 1.1 April 2010 1.0 June 2011 Altera Corporation Changes Made Changed 800 MHz to 1,066 MHz for DDR3 in For Stratix V GT devices, changed 14.1 Gbps to 12.5 Gbps. ■ Changed Configuration via PCIe to Configuration via Protocol ■ ...

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... Stratix V Device Handbook Chapter 1: Stratix V Device Family Overview Revision History June 2011 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... AC input voltage 4 4.05 4.1 4.15 4.2 Electrical Characteristics Minimum Maximum Unit -0.5 3.9 V -0.5 3.75 V -0.5 3.75 V -0.5 4 -55 125 °C -65 150 °C Table 2–2 and Overshoot Duration as % Unit @ T = 100°C J 100 % May 2011 Altera Corporation ...

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... If you do not use the design security feature in Stratix V devices, connect V monitors V . Stratix V devices will not exit POR if V CCBAT (3) Each power supply must reach the recommended operating range within 200 µs. May 2011 Altera Corporation Table 2–3 lists the steady-state voltage and current values expected Condition Minimum — ...

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... Stratix V I/O pin leakage current specifications. Table 2–5. I/O Pin Leakage Current for Stratix V Devices—Preliminary Symbol I Input pin I I Tri-stated I/O pin OZ May 2011 Altera Corporation Description Minimum 2.85, 2.375 0.82 0.82 0.82, 0.95 0.82, 0.95 1.425 and the ...

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... Internal series termination 48--and with calibration (48- 80- 60-and 80- setting) Internal parallel 50- R termination with T calibration (50- setting) May 2011 Altera Corporation V 1.2 V 1.5 V 1.8 V Min Max Min Max Min 22.5 — ...

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... Chapter 2: DC and Switching Characteristics for Stratix V Devices Conditions 1.5, 1.35, CCIO -10 to +40 -10 to +40 -10 to +40 1. 1.2 -10 to +40 -10 to +40 -10 to +40 CCIO V = 3.0, 2.5, 1.8, CCIO ±15 1.5, 1.2 V S_left_shift Electrical Characteristics (Note 1) Calibration Accuracy Unit C3,I3 C4, ±15 ±15 % May 2011 Altera Corporation ...

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... R without calibration (50- S setting) Internal differential 100- termination (100- setting) Note to Table 2–8: (1) Pending silicon characterization. May 2011 Altera Corporation Table 2–8 lists the Stratix V OCT Resistance Tolerance Conditions C2 C3, 3.0 and 2.5 V ±30 CCIO V = 1.8 and 1.5 V ± ...

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... Table 2–9. OCT Variation after Power-Up Calibration for Stratix V Devices—Preliminary (Note 1), (2) Symbol dR/dV dR/dT Notes to Table 2–9: (1) Valid for a V (2) Pending silicon characterization. May 2011 Altera Corporation Table 2–9 to determine the OCT variation after power-up calibration to determine the OCT variation without re-calibration. (6)  dR   ------ - R R ...

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... The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is  approximately 25 k (3) Pin pull-up resistance values may be lower if an external source drives the pin higher than V May 2011 Altera Corporation Description Description DC current per I/O pin ...

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... Class I, II SSTL 12 1.14 1.20 Class I, II HSTL-18 1.71 1.8 Class I, II HSTL-15 1.425 1.5 Class I, II May 2011 Altera Corporation Table 2–18 list the input voltage (V ), and current drive characteristics (I and V OL and I , respectively Table 2–13 2–30. V (V) V ...

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... HSTL- REF — Class II 0.1 HSTL- REF -0.15 Class I 0.08 0.08 HSTL- REF -0.15 Class II 0.08 0.08 May 2011 Altera Corporation V (V) REF Max Min Typ 0.47 * 1.26 0 CCIO V CCIO 0.49 * 1.3 0 CCIO V CCIO V (V) V (V) V (V) IH(DC) IL(AC) IH(AC) ...

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... Typ Max HSTL-18 1.71 1.8 1.89 Class I, II HSTL-15 1.425 1.5 1.575 Class I, II HSTL-12 1.14 1.2 1.26 Class I, II HSUL-12 1.14 1.2 1.3 May 2011 Altera Corporation V (V) V (V) V (V) IH(DC) IL(AC) IH(AC) Min Max Max Min + V - REF REF — ...

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... Mbps, the minimum input voltage is 0.85 V; the maximum input voltage is 1.75 V. For F MAX 0.45 V; the maximum input voltage is 1.95 V. Power Consumption Altera offers two ways to estimate power consumption for a design—the Excel-based Early Power Estimator and the Quartus 1 You typically use the interactive Excel-based Early Power Estimator before designing the FPGA to get a magnitude estimate of the device power ...

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... ICM HCSL I/O standard for V (DC coupled) ICM PCIe reference clock R — REF Transceiver Clocks fixedclk clock PCIe frequency Receiver Detect May 2011 Altera Corporation –1 Commercial Commercial/Industrial Speed Grade Speed Grade Min Typ Max Min 40 — 710 40 45 — ® ...

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... DC Gain Setting = 0 DC Gain Setting = 1 DC Gain Setting Programmable DC gain = 2 DC Gain Setting = 3 DC Gain Setting = 4 May 2011 Altera Corporation –1 –2 Commercial Commercial/Industrial Speed Grade Speed Grade Min Typ Max Min Typ < 150 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS 600 — ...

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... PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about device ordering codes, refer to the (2) The reference clock common mode voltage is equal to the V (3) The device cannot tolerate prolonged operation at this absolute maximum ...

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... Output frequency for an external clock output (–4 speed grade) t Duty cycle for an external clock output (when set to 50%) OUTDUTY t External feedback clock compensation time FCOMP May 2011 Altera Corporation Performance –2 Speed Grade –3 Speed Grade 717 700 550 500 Parameter ...

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... Period Jitter for a dedicated clock output in cascaded PLLs (F < 100 MHz) OUT Frequency drift after PFDENA is disabled for a duration of f DRIFT 100 µs dK Bit number of Delta Sigma Modulator (DSM) BIT k Numerator of Fraction VALUE May 2011 Altera Corporation Parameter Min — ...

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... Modes using Two DSPs Three 18 × 18 One sum of four 18 × 18 One sum of two 27 × 27 One sum of two 36 × 18 One complex 18 × 18 One 36 × 36 Modes using Three DSPs One complex 18 × 25 May 2011 Altera Corporation Parameter Min = 100 MHz) — INPFD the PLL. MAX OUT – ...

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... To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes. (3) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in F May 2011 Altera Corporation Performance –2 – ...

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... Actual achievable frequency depends on design- and system-specific factors. You must perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. May 2011 Altera Corporation Description TCK clock period TCK clock high time TCK clock low time ...

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... Total Jitter for Data Rate Output Resistor < 600 Mbps Network Transmitter output clock duty cycle for both True and t DUTY Emulated Differential I/O Standards May 2011 Altera Corporation (Note 1), (2), (3) –2 Speed Grade –3 Speed Grade Min Typ Max Min Typ ...

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... If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps. May 2011 Altera Corporation (Note 1), (2), (3) –2 Speed Grade – ...

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... One data transition is defined as a 0-to-1 or 1-to-0 transition. (3) The DPA lock time stated in this table applies to both commercial and industrial grade. (4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions. May 2011 Altera Corporation DPA Lock Time 256 data ...

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... F2 F1 Table 2–28. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to or Higher than 1.25 Gbps—Preliminary May 2011 Altera Corporation F3 Jitter Frequency (Hz) Jitter Frequency (Hz) 10,000 17,565 1,493,000 50,000,000 Stratix V Device Handbook Volume 1: Overview and Datasheet 2–25 Table 2–28 ...

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... The delay settings are linear with a cumulative delay variation for all speed grades. For example, when using a –2 speed grade and applying a 10-phase offset setting to a 90° phase shift at 400 MHz, the expected average cumulative delay is [625 ps + (10 × 10 ps) ± 20 ps] = 725 ps ± 20 ps. May 2011 Altera Corporation 20db/dec baud/1667 ...

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... The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard. (3) The clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible. May 2011 Altera Corporation ...

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... The numbers are preliminary pending silicon characterization. I/O Timing Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the Quartus II Timing Analyzer. Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis ...

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... You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment. May 2011 Altera Corporation (Note 1) Fast Model ...

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... Left and right PLL input clock frequency. HSCLK High-speed I/O block—Maximum and minimum LVDS data transfer rate f HSDR 1/TUI), non-DPA. HSDR High-speed I/O block—Maximum and minimum LVDS data transfer rate f HSDRDPA (f HSDRDPA G H — I May 2011 Altera Corporation Definitions — — = 1/TUI), DPA. — ...

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... Diagram of PLL Specifications CLK Core Clock PLL P Specifications Key Note: (1) Core Clock can only be fed by dedicated clock input pins or PLL outputs. Q — Receiver differential input discrete resistor (external to the Stratix V device). L May 2011 Altera Corporation Definitions t JCP JCH JCL JPSU JPH t t JPZX JPCO — ...

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... Signal low-to-high transition time (20-80%) RISE U — Stratix V Device Handbook Volume 1: Overview and Datasheet Chapter 2: DC and Switching Characteristics for Stratix V Devices Definitions Bit Time Sampling Window RSKM RSKM 0.5 x TCCS (SW) V REF — Glossary V CCIO IH(DC) V IL(DC) V IL( variation CO /w) C May 2011 Altera Corporation ...

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... Updated Table 1–2, Table 1–4, Table 1–19, and Table 1–23. ■ December 2010 1.1 Converted chapter to the new template. ■ Minor text edits. ■ July 2010 1.0 Initial release. May 2011 Altera Corporation Definitions — Changes Table 2–4, Table 2–18, Table 2–19, Table 2– ...

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... Stratix V Device Handbook Volume 1: Overview and Datasheet Chapter 2: DC and Switching Characteristics for Stratix V Devices Document Revision History May 2011 Altera Corporation ...

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... Technical training Product literature Non-technical support (General) (Software Licensing) Note to Table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions this document uses. Visual Cue Bold Type with Initial Capital ...

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... A warning calls attention to a condition or possible situation that can cause you injury. The envelope links to the Email Subscription Management Center website, where you can sign up to receive update notifications for Altera documents. Additional Information Typographic Conventions page of the Altera June 2011 Altera Corporation ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Volume 2: Device Interfaces and Integration 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V1-1.3 11.0 Stratix V Device Handbook ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Read/Write Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Selecting Embedded Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Read-During-Write Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17 Same-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18 Mixed-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19 May 2011 Altera Corporation Stratix V Device Handbook Volume 2: Device Interfaces and Integration Contents ...

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... Clock Input Pin Connections to GCLK and RCLK Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Clock Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13 Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13 Clock Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16 Stratix V PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17 Fractional PLL Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23 Fractional PLL Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23 Stratix V Device Handbook Volume 2: Device Interfaces and Integration Contents May 2011 Altera Corporation ...

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... OCT Calibration Block Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22 Power-Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22 OCT Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–23 Serial Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–24 Example of Using Multiple OCT Calibration Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–25 Termination Schemes for I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–25 May 2011 Altera Corporation Stratix V Device Handbook Volume 2: Device Interfaces and Integration v ...

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... Memory Interface Pin Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3 Using the RZQ Pins in a DQ/DQS Group for Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 Stratix V External Memory Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 DQS Phase-Shift Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–8 Stratix V Device Handbook Volume 2: Device Interfaces and Integration ) and Programmable Pre-Emphasis . . . . . . . . . . . 6–9 OD May 2011 Altera Corporation Contents ...

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... Active Serial Configuration (Serial Configuration Devices 9–16 AS Multi-Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–19 AS Connection Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–22 AS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–22 Estimating the Active Serial Configuration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23 Programming EPCS and EPCQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–23 Passive Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–28 May 2011 Altera Corporation Stratix V Device Handbook Volume 2: Device Interfaces and Integration vii ...

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... Chapter 12. Power Management in Stratix V Devices Stratix V Programmable Power Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 Stratix V External Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–3 Temperature Sensing Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–3 Internal Temperature Sensing Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 External Temperature Sensing Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 Stratix V Device Handbook Volume 2: Device Interfaces and Integration Contents May 2011 Altera Corporation ...

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... Contents Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6 Additional Information How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 May 2011 Altera Corporation Stratix V Device Handbook Volume 2: Device Interfaces and Integration ix ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Contents May 2011 Altera Corporation ...

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... Chapter 10. SEU Mitigation in Stratix V Devices Revised: Part Number: SV51011-1.2 Chapter 11. JTAG Boundary-Scan Testing in Stratix V Devices Revised: Part Number: SV51012-1.2 Chapter 12. Power Management in Stratix V Devices May 2011 Altera Corporation May 2011 May 2011 May 2011 May 2011 May 2011 May 2011 May 2011 ...

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... Revised: Part Number: SV51013-1.2 Stratix V Device Handbook Volume 2: Device Interfaces and Integration May 2011 Chapter Revision Dates May 2011 Altera Corporation ...

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... Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. May 2011 Altera Corporation Section I. Device Core ® V device family core, which is the most ...

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... I–2 Stratix V Device Handbook Volume 2: Device Interfaces and Integration Section I: Device Core May 2011 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Simple dual-port SRAM (1) LUT-based- Simple dual-port SRAM (1) LUT-based- Simple dual-port SRAM (1) LUT-based- Simple dual-port SRAM LUT-based- (1) Simple dual-port SRAM MLAB Logic Array Blocks Figure 1–2. The ALM ALM ALM ALM ALM ALM ALM ALM ALM ALM LAB May 2011 Altera Corporation ...

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... For example, any ALM in a particular LAB using the labclk1 signal also uses the labclkena1 signal. If the LAB uses both the rising and falling edges of a clock, it also uses two LAB-wide clock signals. Deasserting the clock enable signal turns off the corresponding LAB-wide clock. May 2011 Altera Corporation Local Interconnect LAB Stratix V Device Handbook Volume 2: Device Interfaces and Integration 1– ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices There are two unique clock signals per LAB. labclk0 labclk1 labclk2 labclkena0 labclkena1 labclkena2 or asyncload or labpreset Adaptive Logic Modules labclr1 syncload labclr0 synclr May 2011 Altera Corporation ...

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... Figure 1–5. High-Level Block Diagram of the Stratix V ALM shared_arith_in Combinational/Memory ALUT0 dataf0 6-Input LUT datae0 dataa datab datac datad 6-Input LUT datae1 dataf1 Combinational/Memory ALUT1 shared_arith_out May 2011 Altera Corporation Figure 1–5 shows a high-level block diagram of the Stratix V reg_chain_in carry_in labclk D adder0 reg0 D reg1 D adder1 reg2 D ...

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Figure 1–6 shows a detailed view of all the connections in an ALM. Figure 1–6. ALM Connection Details for Stratix V Devices ...

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... Normal mode allows two functions to be implemented in one Stratix V ALM single function six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs. May 2011 Altera Corporation 1–3. Stratix V Device Handbook Volume 2: Device Interfaces and Integration 1–7 ...

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... LUT dataf0 datae0 dataa datab datac 5-Input datad combout0 LUT 4-Input combout1 datae1 LUT dataf1 Adaptive Logic Modules 5-Input combout0 LUT 5-Input combout1 LUT 6-Input combout0 LUT 6-Input combout0 LUT 6-Input combout1 LUT May 2011 Altera Corporation ...

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... Figure 1–9. Template for Supported Seven-Input Functions in Extended LUT Mode Note to Figure 1–9: (1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available. May 2011 Altera Corporation (Figure 1–8). If you use datae1 and dataf1, the (Note 1) dataf0 datae0 ...

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... Adaptive Logic Modules Figure 1–10, the carry-in To general or local routing To general local routing reg0 To general or local routing To general local routing reg1 To general or local routing To general local routing reg2 To general or local routing To general local routing reg3 May 2011 Altera Corporation ...

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... ALM in the LAB) using a dedicated connection called the shared arithmetic chain. This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree. May 2011 Altera Corporation “ALM Interconnects” Stratix V Device Handbook Volume 2: Device Interfaces and Integration 1–11 ...

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... LUT shared_arith_out carry_out 1–14. Adaptive Logic Modules To general or local routing To general local routing reg0 To general or local routing To general local routing reg1 To general or local routing To general local routing reg2 To general or local routing To general local routing reg3 “ALM May 2011 Altera Corporation ...

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... Figure 1–12: (1) You can use the combinational or adder logic to implement an unrelated, un-registered function. For more information about the register-chain interconnect, refer to Interconnects” on page May 2011 Altera Corporation Figure 1–12). The Quartus II Compiler automatically takes (Note 1) From previous ALM within the LAB ...

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... Local interconnect routing among ALMs in the LAB ALM 1 Carry chain and shared arithmetic chain routing to adjacent ALM ALM 2 Local ALM 3 interconnect ALM 4 ALM 5 ALM 6 ALM 7 ALM 8 ALM 9 ALM 10 Adaptive Logic Modules Register chain routing to adjacent ALM's register input May 2011 Altera Corporation ...

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... December 2010 1.1 No changes to the content of this chapter for the Quartus II software 10.1. July 2010 1.0 Initial release. May 2011 Altera Corporation Power Optimization chapter in volume 2 of the Quartus II Changes Figure 1–6. Stratix V Device Handbook Volume 2: Device Interfaces and Integration ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 1: Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices Document Revision History May 2011 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... Outputs set to old data or don’t care Built-in support in x32-wide simple dual-port mode or soft IP support using the Quartus II software Total RAM Bits (Including LABs) (Mb) 17.9 29.8 49.9 57.2 61.2 62.5 46.7 58.8 49.9 57.2 10.3 16.2 24.6 44.6 52.0 59.4 May 2011 Altera Corporation ...

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... Table 2–3. byteena Controls in x40 Data Width byteena[3..0] 1111(default) 1000 0100 0010 0001 May 2011 Altera Corporation Total Dedicated RAM Bits M20K Blocks (M20K Blocks Only) (Mb) 2,640 51.6 2,640 51.6 Data Bits Written ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration [19:10] [19:10 — ABCDEF12 1000 0100 0010 0001 ABFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF ABXXXXXX XXCDXXXX XXXXEFXX Chapter 2: Memory Blocks in Stratix V Devices Overview Data Bits Written [9:0] — [9: XXXXXXXX 1111 XXXX FFCDFFFF FFFFEFFF FFFFFF12 ABCDEF12 ABCDEF12 XXXXXX12 ABFFFFFF May 2011 Altera Corporation ...

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... The default value for the address clock enable signal is low (disabled). Figure 2–2 shows an address clock enable block diagram. The address clock enable is referred to by the port name addressstall. Figure 2–2. Address Clock Enable May 2011 Altera Corporation 1 address[0] address[0] 0 register ...

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... MLABs do not support mixed-width FIFO mode. Stratix V Device Handbook Volume 2: Device Interfaces and Integration doutn dout0 dout1 dout0 dout1 Chapter 2: Memory Blocks in Stratix V Devices Overview dout4 dout4 dout5 “Memory Modes” on May 2011 Altera Corporation ...

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... The status flags are part of the regular output from the memory block. When ECC is engaged, you cannot access two of the parity bits because they are replaced by the ECC status flag. May 2011 Altera Corporation Stratix V Device Handbook Volume 2: Device Interfaces and Integration ...

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... An uncorrectable error occurred and uncorrectable 1 data appears at the outputs Optional 40 Memory Pipeline Array Register (only supported on M20K) Chapter 2: Memory Blocks in Stratix V Devices Memory Modes Status 2 Status Flag Generation ECC Output Decoder Register May 2011 Altera Corporation ...

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... RAM outputs show the “new data” being written. Table 2–6 lists the possible port width configurations for embedded memory blocks in single-port mode. Table 2–6. Port Width Configurations for MLABs and M20K (Single-Port Mode) May 2011 Altera Corporation (Note 1) data[] address[] wren ...

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... M20K blocks in simple Write Port — — — — Chapter 2: Memory Blocks in Stratix V Devices Memory Modes A1 EEEE FFFF EEEE FFFF (Note 1) rdaddress[ ] rden q[ ] rdclock rdclocken ecc_status aclr 512 x 32 512 — — May 2011 Altera Corporation — — ...

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... Registering the RAM outputs delay the q output by one clock cycle. Figure 2–10. Simple Dual-Port Timing Waveforms wrclock wren an wraddress an-1 data din-1 din rdclock rden rdaddress bn q (asynch) doutn-1 May 2011 Altera Corporation Write Port — — — — — — ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration dout0 doutn data_a[] data_b[] address_a[] address_b[] wren_a wren_b byteena_a[] byteena_b[] addressstall_a addressstall_b clock_a clock_b rden_a rden_b aclr_a aclr_b q_a[] q_b[] Chapter 2: Memory Blocks in Stratix V Devices Memory Modes din4 din5 din6 b2 b3 May 2011 Altera Corporation ...

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... This results in unknown data being stored to that address location. No conflict resolution circuitry is built into the Stratix V embedded memory blocks. You must resolve address conflicts external to the RAM block. May 2011 Altera Corporation Port ...

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... You can cascade memory blocks to implement larger shift registers. Stratix V Device Handbook Volume 2: Device Interfaces and Integration dout0 dout1 dout2 din b1 b0 doutn dout0 Chapter 2: Memory Blocks in Stratix V Devices Memory Modes din4 din5 din6 dout3 din5 din4 b2 b3 dout2 dout1 May 2011 Altera Corporation ...

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... Plug-In Manager to implement FIFO buffers in your design. The FIFO MegaWizard Plug-In Manager supports single- and dual-clock (asynchronous) FIFO buffers. f For more information about implementing FIFO buffers, refer to the DCFIFO Megafunctions User 1 MLABs do not support mixed-width FIFO mode. May 2011 Altera Corporation Guide. Stratix V Device Handbook Volume 2: Device Interfaces and Integration 2– ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 2: Memory Blocks in Stratix V Devices Simple Dual-Port Mode Single-Port Mode — — — Clocking Modes ROM Mode FIFO Mode v — v — v — May 2011 Altera Corporation ...

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... You can customize the read-during-write behavior of the Stratix V embedded memory blocks to suit your design requirements. There are two types of read-during-write operations—same port and mixed port. May 2011 Altera Corporation Logic Array Blocks and chapter. Stratix V Device Handbook Volume 2: Device Interfaces and Integration ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Port A data in Port A data out 0A 11 A123 B456 C789 DDDD A123 B456 C789 DDDD Chapter 2: Memory Blocks in Stratix V Devices Design Considerations Port B data in Mixed-port data flow Same-port data flow Port B data out 0B EEEE FFFF EEEE FFFF May 2011 Altera Corporation ...

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... Figure 2–17. Mixed-Port Read-During-Write—Old Data Mode clk_a&b wren_a address_a data_a byteena_a rden_b address_b q_b (asynch) May 2011 Altera Corporation Internal Memory (RAM and ROM) Megafunction User A0 AAAA BBBB CCCC DDDD 11 A0 AAAA BBBB ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration A0 AAAA BBBB CCCC DDDD XXXX (unknown data) and the Quartus II Handbook. Chapter 2: Memory Blocks in Stratix V Devices Design Considerations A1 EEEE FFFF 11 A1 Internal Memory (RAM and ROM) May 2011 Altera Corporation ...

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... Table 2–10. Document Revision History Date Version May 2011 1.2 December 2010 1.1 July 2010 1.0 May 2011 Altera Corporation Changes Chapter moved to volume 2 for the 11.0 release. ■ Updated Table 2–1, Table 2–2, and Table ■ ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 2: Memory Blocks in Stratix V Devices Document Revision History May 2011 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... May 2011 Altera Corporation ...

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... Two Multiplier Adder Two Multiplier Adder 3 variable precision Complex Multiplication DSP blocks 4 variable precision Complex Multiplication DSP blocks Note to Table 3–2: (1) The pre-adder feature for this mode is automatically enabled. May 2011 Altera Corporation Supported Pre-adder Coefficient Instance Support Support Yes Yes ...

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... II software includes megafunctions that you can use to control the ™ Plug-In Manager, the Quartus II software automatically CLK[2..0] ENA[2..0] chainin[63..0] ACLR[1..0] Mult_L Systolic Registers x +/- +/- +/- Mult_H x Adder Variable Precision DSP Block Resource Descriptions Constant Systolic Register + Chainout adder/ accumulator 64 chainout[63..0] May 2011 Altera Corporation Result[65..0] ...

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... The delay registers are used to balance the latency requirements when both the input cascade and chainout features are used. This is only supported mode. May 2011 Altera Corporation Stratix V Device Handbook Volume 2: Device Interfaces and Integration 3–5 ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 3: Variable Precision DSP Blocks in Stratix V Devices Variable Precision DSP Block Resource Descriptions Figure 3–2 and Figure 3–3. The Stratix V variable precision DSP CLK[2..0] ENA[2..0] scanin[18..0] ACLR[0] Delay registers Delay registers scanout[18..0] May 2011 Altera Corporation ...

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... If the multiplicand input comes from internal coefficient, the data width of the input is 27 bits. 1 When you enable the pre-adder feature, all input data and multipliers must have the same clock setting. May 2011 Altera Corporation scanin[26..0] datab_0[26..0] dataa_0[26..0] datac_0[24..0] Stratix V Device Handbook Volume 2: Device Interfaces and Integration 3– ...

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... FIR mode, both systolic registers are bypassed. Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 3: Variable Precision DSP Blocks in Stratix V Devices Variable Precision DSP Block Resource Descriptions 3–9. Description Table 3–4 lists how these dynamic NEGATE LOADCONST “Operational Mode ACCUMULATE May 2011 Altera Corporation ...

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... For some operational modes, the unused inputs require zero padding. May 2011 Altera Corporation Stratix V Device Handbook Volume 2: Device Interfaces and Integration 3–9 ...

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... Chapter 3: Variable Precision DSP Blocks in Stratix V Devices 3–5, Figure 3–7 on page 3–12, Figure 3–8 on page show the variable precision DSP block in independent Figure 3–6 on page 3–11 shows that two variable precision (Note 1) Multiplier x Mult_L x Operational Mode Descriptions 3–12, and 54 result[53..0] (p2, p1, p0) 36 result[35..0] May 2011 Altera Corporation ...

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... Variable Precision DSP Block 1 18 datab_2[17..0] 18 dataa_2[17..0] 18 datab_1[17..0] 18 dataa_1[17..0] May 2011 Altera Corporation Mult_L x Mult_L x Mult_L x Mult_H x Variable Precision DSP Block 2 Stratix V Device Handbook Volume 2: Device Interfaces and Integration 3–11 36 result_0[35..0] 18 result_2[17..0] 18 result_2[35 ...

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... Figure 3–8: (1) The result can 64-bits when combined with a chainout adder/accumulator. Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 3: Variable Precision DSP Blocks in Stratix V Devices Mult_L x Mult_H x (Note 1) Multiplier 54 x Operational Mode Descriptions result_0[ ] result_1[ ] Result[53..0] May 2011 Altera Corporation ...

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... Figure 3–10. 36-Bit Independent Multiplier Mode with Two Variable Precision DSP Blocks for Stratix V Devices datab_0[17..0] dataa_0[17..0] datab_0[17..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] May 2011 Altera Corporation x Mult_L +/- x Mult_H Figure 3–10. The 36-bit multiplier is useful for Mult_L Adder ...

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... Chapter 3: Variable Precision DSP Blocks in Stratix V Devices Equation 3–1 shows a complex multiplication that you can write jb) × jd) = [(a × × d)] + j[(a × × c)] Mult_L Adder x + Mult_H x Mult_L Adder x + Mult_H x Operational Mode Descriptions 37 Imaginary part (ad + bc) 37 Real part ( May 2011 Altera Corporation ...

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... Variable Precision DSP Block 2 18 d[17..0] 18 c[17..0] 25 a[24..0] Variable Precision DSP Block 3 May 2011 Altera Corporation Equation 3–2. Multiplier x Multiplier Chainout Adder x Multiplier Chainout Adder x Stratix V Device Handbook Volume 2: Device Interfaces and Integration 3–15 ...

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... Variable Precision DSP Block 4 Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 3: Variable Precision DSP Blocks in Stratix V Devices Multiplier x Multiplier Chainout Adder Multiplier x Multiplier Chainout Adder Operational Mode Descriptions [(a × × c)] [(a × × d)] May 2011 Altera Corporation ...

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... For 18-bit multiplier adder sum mode, the input data width is 18 bits and the output data width is 37 bits. (2) For 16-bit multiplier adder sum mode, the input data width is 16 bits and the unused input bit requires padding with zeroes. The output data width is 33 bits. May 2011 Altera Corporation Figure 3–14 through Figure 3– ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 3: Variable Precision DSP Blocks in Stratix V Devices Multiplier x Chainout[53..0] Chainout adder/ Multiplier accumulator x +/- + Multiplier Adder +/- x Variable Precision DSP Block 1 Multiplier Chainout Adder Adder + +/- +/- x Variable Precision DSP Block 2 Operational Mode Descriptions 55 Result[54..0] 54 result[54..0] May 2011 Altera Corporation ...

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... Variable Precision DSP Block 1 SUB_COMPLEX 19 datab_2[17..0] 18 dataa_2[17..0] 19 datab_3[17..0] 18 dataa_3[17..0] NEGATE Variable Precision DSP Block 2 May 2011 Altera Corporation Mult_L x +/- Mult_H x Adder Chainout[38..0] Mult_L x Chainout adder/ accumulator +/- +/- + Mult_H x Adder Stratix V Device Handbook Volume 2: Device Interfaces and Integration 3– ...

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... Chapter 3: Variable Precision DSP Blocks in Stratix V Devices 2 . You can feed the four 18-bit inputs into the pre-adder block to Pre-Adder Multiplier 18 +/- x 18 Adder +/- Pre-Adder Multiplier 18 x +/- 18 Variable Precision DSP Block Figure 3–19 Mult_L x +/- Adder Operational Mode Descriptions 37 result[36..0] shows the multiplication 37 Result[36..0] May 2011 Altera Corporation ...

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... Figure 3–20. 18-bit Systolic FIR Mode with Two Dynamic Inputs for Stratix V Devices Pre-Adder 18 datab_0[17..0] +/- 18 dataa_0[17..0] 3 COEFSELA[2..0] Coefficient Pre-Adder 18 datab_1[17..0] +/- 18 dataa_1[17..0] 3 COEFSELB[2..0] Coefficient May 2011 Altera Corporation Mult_L Systolic Registers x +/- +/- Internal Adder Mult_H x Internal 18-bit Systolic FIR Stratix V Device Handbook Volume 2: Device Interfaces and Integration 3–21 chainin[43..0] Systolic Register + ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 3: Variable Precision DSP Blocks in Stratix V Devices lists the variable precision DSP block dynamic signals. The Function x 18 multiplier results x 36 mode and complex Total Count per DSP Block Operational Mode Descriptions Count May 2011 Altera Corporation ...

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... Chapter 3: Variable Precision DSP Blocks in Stratix V Devices Software Support Software Support Altera provides two methods for implementing various modes of the Stratix V variable precision DSP block in a design: Using the Quartus II software and HDL inferring. The following Quartus II megafunctions are supported for the ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 3: Variable Precision DSP Blocks in Stratix V Devices Document Revision History May 2011 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

Page 142

... GCLK[0..3] Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 4: Clock Networks and PLLs in Stratix V Devices Table 4–2 on page 4–9 and Table 4–3 on page 4–10 Guidelines. GCLK[12..15] GCLK[8..11 GCLK[4..7] Clock Networks in Stratix V Devices list the clock Stratix V May 2011 Altera Corporation ...

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... I/O pins, and internal logic can drive the PCLK networks. PCLKs have higher skew when compared with GCLK and RCLK networks. You can use PCLKs for general purpose routing to drive signals into and out of the Stratix V device. May 2011 Altera Corporation RCLK[9..0] RCLK[19..10] RCLK[51..46] RCLK[77..71] ...

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... Chapter 4: Clock Networks and PLLs in Stratix V Devices Vertical Vertical PCLK[0..19] PCLK[86..105] Horizontal PCLK[84..95] Horizontal PCLK[72..83 Horizontal PCLK[60..71] Horizontal PCLK[48..59] Vertical PCLK[66..85] Vertical Vertical PCLK[0..20] PCLK[96..115] Horizontal PCLK[116..131] Horizontal PCLK[98..115 Horizontal PCLK[66..81] Vertical PCLK[76..95] Clock Networks in Stratix V Devices Horizontal PCLK[82..97] May 2011 Altera Corporation ...

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... PCLK[17..32] Horizontal PCLK[33..48] Horizontal PCLK[49..65] Vertical PCLK[26..51] Figure 4–6. PCLK Networks—5SGSD6 and 5SGSD8 Devices Horizontal PCLK[0..17] Horizontal PCLK[18..35] Horizontal PCLK[36..53] Horizontal PCLK[54..71] May 2011 Altera Corporation Vertical Vertical PCLK[0..25] PCLK[113..138 Vertical PCLK[87..112] Vertical Vertical PCLK[0..23] PCLK[102..120] Horizontal PCLK[135 ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 4: Clock Networks and PLLs in Stratix V Devices Figure 4–7 16 GCLK 5 (4) SCLK 33 83 (2) PCLK 23 (3) RCLK Clock Networks in Stratix V Devices shows SCLKs driven by the (Note 1) 9 Column I/O clock (5) 2 Core reference clock (6) 6 Row clock (7) May 2011 Altera Corporation ...

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... Corner PLL outputs only span one quadrant, they cannot generate a dual-regional clock network. Figure 4–8 shows the dual-regional clock region. Figure 4–8. Dual-Regional Clock Region for Stratix V Devices May 2011 Altera Corporation Clock pins or PLL outputs can drive half of the device to create dual-regional clocking regions for improved interface timing ...

Page 148

... Stratix V PLL clock outputs can drive both GCLK and RCLK networks. Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 4: Clock Networks and PLLs in Stratix V Devices Table 4–3 on page 4–10. chapter. Clock Networks in Stratix V Devices High-Speed Differential May 2011 Altera Corporation ...

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Clock Input Pin Connections to GCLK and RCLK Networks Table 4–2 lists the connection between the dedicated clock input pins and GCLKs. Table 4–2. Clock Input Pin Connectivity to the GCLK Networks—Preliminary Clock Resources ...

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Table 4–3 lists the connectivity between the dedicated clock input pins and RCLKs in Stratix V devices. A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network. Table 4–3. Clock Input Pin Connectivity ...

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Table 4–3. Clock Input Pin Connectivity to the RCLK Networks (Part 2 of 3)—Preliminary Clock Resources RCLK — — — — — — — — [52,53,54,55,56, 57,74,81] RCLK — — — — — — ...

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Table 4–3. Clock Input Pin Connectivity to the RCLK Networks (Part 3 of 3)—Preliminary Clock Resources RCLK — — — — — — — — [40,41,42,43,44, 45,67,88] RCLK [71,75,78,82] — — — — — ...

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... You can set the input clock sources and the clkena signals for the GCLK and RCLK network multiplexers through the Quartus II software using the ALTCLKCTRL megafunction. May 2011 Altera Corporation Devices. 4–10, and Figure 4–11 ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 4: Clock Networks and PLLs in Stratix V Devices Clock Control Block (ALTCLKCTRL) Megafunction CLKp CLKn (2) Pin Pin PLL Counter 2 Internal Outputs Logic Static Clock Select (1) Enable/ Disable Internal Logic RCLK Clock Networks in Stratix V Devices May 2011 Altera Corporation ...

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... GCLK and RCLK networks, including dual-regional clock regions. Figure 4–10 show that this function is independent of the PLL and is applied directly on the clock network. May 2011 Altera Corporation HSSI output or DPA clock output Internal logic Static Clock Select ...

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... Chapter 4: Clock Networks and PLLs in Stratix V Devices Figure 4–12 shows the external PLL output clock PLL Counter Outputs 18 Static Clock Select Enable/ Disable Internal Logic IOE (2) Internal Logic Static Clock Select (1) FPLL_<#>_CLKOUT pin (1) (1) ( Clock Networks in Stratix V Devices (1) GCLK/ RCLK/ FPLL_<#>_CLKOUT (1) May 2011 Altera Corporation ...

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... Stratix V devices offer fractional PLLs in the larger densities. All Stratix V fractional PLLs have the same core analog structure and features support. May 2011 Altera Corporation Figure 4–14 shows a waveform example for Stratix V Device Handbook Volume 2: Device Interfaces and Integration ...

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... Chapter 4: Clock Networks and PLLs in Stratix V Devices Feature 4 single-ended or 2 single-ended and 4 single-ended or 4 differential Stratix V PLLs Stratix V Yes Yes 512 1 differential Single-ended or differential Yes (1) Yes Yes Yes Yes Yes Yes Yes 78.125 ps (2) Yes ° . Smaller degree May 2011 Altera Corporation ...

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... CLK0, CLK1, CLK20, and CLK21 clock pins feed into fractional PLL LR_X0_Y37 and fractional PLL LR_X0_Y46. (3) CLK8, CLK9, CLK12, and CLK13 clock pins feed into fractional PLL LR_X152_Y37 and fractional PLL LR_X152_Y46. May 2011 Altera Corporation Figure 4–18 on page 4–22 show the physical locations of the (Note 1) CLK[16 ...

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... CEN_X90_Y11 CEN_X90_Y2 4 Logical clocks Logical clocks 4 Logical clocks 4 Pins Pins CLK[0..3][p,n] CLK[4..7][p,n] CLK[8..11][p,n] Stratix V PLLs Pins Logical clocks LR_X197_Y109 4 LR_X197_Y100 LR_X197_Y85 4 LR_X197_Y76 (3) 2 LR_X197_Y63 (3) 2 LR_X197_Y54 LR_X197_Y39 4 LR_X197_Y30 LR_X197_Y14 4 LR_X197_Y5 Pins May 2011 Altera Corporation ...

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... COR_X0_Y10 4 COR_X0_Y1 Note to Figure 4–17: (1) Every index represents one fractional PLL in the device. The physical locations of the fractional PLLs correspond to the coordinates in the Quartus II software Chip Planner. May 2011 Altera Corporation (Note 1) CLK[20..23][p,n] CLK[16..19][p,n] CLK[12..15][p,n] Pins Pins Pins ...

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... Pins 4 Logical clocks 4 Logical clocks 4 Logical clocks CEN_X105_Y132 CEN_X105_Y123 5SGSD6 5SGSD8 CEN_X105_Y11 CEN_X105_Y2 4 Logical clocks Logical clocks 4 Logical clocks 4 Pins Pins Pins CLK[4..7][p,n] CLK[8..11][p,n] Stratix V PLLs COR_X218_Y126 COR_X218_Y117 CLK[24..27][p,n] LR_X218_Y70 Pins 4 LR_X218_Y61 COR_X218_Y12 COR_X218_Y3 May 2011 Altera Corporation ...

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... Four single-ended clock outputs and two single-ended feedback inputs within the I/O driver feedback for ZDB support ■ Two single-ended clock outputs and two single-ended feedback inputs for single-ended External Feedback (EFB) support May 2011 Altera Corporation Lock locked Circuit 8 ÷2 ÷ ...

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... EXTCLKOUT[3..0] 4 EXTCLKOUT[2] fbin1 EXTCLKOUT[3] I/O Features in Stratix V Devices chapter. Stratix V PLLs IO/FPLL_<#>_CLKOUT0, FPLL_<#>_CLKOUTp, FPLL_<#>_FB0 (1), (2), (3), (4) IO/FPLL_<#>_CLKOUT1, FPLL_<#>_CLKOUTn (1), (2), (3) IO/FPLL_<#>_CLKOUT2, FPLL_<#>_FBp, FPLL_<#>_FB1 (1), (2), (3), (4) IO/FPLL_<#>_CLKOUT3, FPLL_<#>_FBn (1), (2), (3) May 2011 Altera Corporation ...

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... Altera recommends using the areset and locked signals in your designs to control and observe the status of your PLL. May 2011 Altera Corporation Stratix V Device Handbook Volume 2: Device Interfaces and Integration 4– ...

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... IOE input register. Figure 4–21 shows an example waveform of the clock and data in this mode. Altera recommends source synchronous mode for source-synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard. Figure 4– ...

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... Clock input pin-to-SERDES capture register. In addition, the output counter must provide the 180° phase shift Figure 4–22 shows an example waveform of the clock and data in LVDS mode. Figure 4–22. Phase Relationship Between the Clock and Data in LVDS Mode May 2011 Altera Corporation Data pin PLL reference clock at the input pin ...

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... Input Pin PLL Clock at the Register Clock Port (1) Figure 4–24 shows an example waveform of the PLL clocks’ phase Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port Stratix V PLLs Figure 4–23 shows an example May 2011 Altera Corporation ...

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... I/O standards on the PLL clock input or output pins. Figure 4–25. ZDB Mode in Stratix V PLLs inclk ÷n PFD CP/LF inclk ÷n PFD CP/LF Note to Figure 4–25: (1) ZDB mode can support up to four single-ended clock outputs. For more information, refer to May 2011 Altera Corporation (Note EXTCLKOUT[ VCO 0 EXTCLKOUT[1] C8 ...

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... Left and right PLLs support this mode when using single-ended I/O standards only. Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 4: Clock Networks and PLLs in Stratix V Devices Phase Aligned PLL Reference Clock at the Input Pin Dedicated PLL Clock Outputs Stratix V PLLs May 2011 Altera Corporation ...

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... Figure 4–27. Phase Relationship Between the PLL Clocks in External Feedback Mode Note to Figure 4–27: (1) The PLL clock outputs can lead or lag the fbin clock input. May 2011 Altera Corporation Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at ...

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... C11 C12 C13 EXTCLKOUT[2] C14 C15 C16 C17 m0 EXTCLKOUT[3] m1 (M/N). Each output port has a unique post-scale counter that in Stratix V PLLs fbout[p] fbin0 (3) (4) fbout[n] fbout0 fbin[p] external board fbin1 trace (4) fbin[n] fbout1 (3) Figure 4–20 on page 4–24. May 2011 Altera Corporation ...

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... May 2011 1.2 Figure Updated ■ Added ■ December 2010 1.1 No changes to the content of this chapter for the Quartus II software 10.1. July 2010 1.0 Initial release. May 2011 Altera Corporation Changes Table 4–1. Figure 4–3, Figure 4–4, Figure 4–5, Figure 4–18, Figure 4– ...

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... Stratix V Device Handbook Volume 2: Device Interfaces and Integration Chapter 4: Clock Networks and PLLs in Stratix V Devices Document Revision History May 2011 Altera Corporation ...

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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. May 2011 Altera Corporation Section II. I/O Interfaces ® V device I/O features, external ...

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... II–2 Stratix V Device Handbook Volume 2: Device Interfaces and Integration Section II: I/O Interfaces May 2011 Altera Corporation ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...

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... RLDRAM III QDR II/RLDRAM II QDR II/QDR II+/RLDRAM II General purpose LPDDR2 SDRAM DDR SDRAM DDR2 SDRAM DDR3 SDRAM Clock interfaces Clock interfaces Clock interfaces DDR3 SDRAM DDR3L SDRAM DDR3U SDRAM RLDRAM III LPDDR2 SDRAM High-speed communications Flat panel display May 2011 Altera Corporation ...

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... SSTL-12 HSTL-18 Class I HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II HSTL-12 Class I JESD8-16A HSTL-12 Class II JESD8-16A HSUL-12 Differential SSTL-2 Class I Differential SSTL-2 Class II Differential SSTL-18 Class I May 2011 Altera Corporation I/O Standard (Note 1) (Part (V) CCIO Input Output Operation Operation JESD8-B 3.0/2.5 3.0 JESD8-B 3 ...

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... V. CCPD “3.3-V I/O Interface” on page . Differential HSTL, SSTL, and CCPD . CCPD May 2011 Altera Corporation (V) 5–10. ...

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... This figure illustrates the highest density for Stratix V devices. More information about other Stratix V devices bank locations will be available in future releases of the Stratix V device pin-out files. Bank 3A Bank 3B Bank 3C May 2011 Altera Corporation Bank 8D Bank 8E Bank 7E Bank 7D Bank 7C ...

Page 182

... KF1517 NF1932 — — — — — — 696, 175, 36 — 696, 175, 36 — — 696, 175, 36 900, 225, 48 — 696, 175, 36 900, 225, 48 (Note 1)—Preliminary KF1517 F1932 — — — 840, 210, 0 — 840, 210, 0 May 2011 Altera Corporation ...

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... RF1517 5SGXB6 36 48 — — 5SGXB5 RF1760 5SGXB6 5SGXA5 5SGXA7 HF1932 5SGXA9 5SGXAB May 2011 Altera Corporation Table 5–8 list the modular I/O banks for Stratix V devices. Bank — 24 — — 24 — 24 — — 24 — — 24 — 24 — — — — ...

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... May 2011 Altera Corporation 240 240 396 396 396 492 552 552 696 696 696 696 900 900 588 588 552 552 696 696 840 840 ...

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... Rate Block Core DQS D4 Delay CQn clkin Notes to Figure 5–2: (1) The D3_0 and D3_1 delays have the same available settings in the Quartus II software. (2) One dynamic OCT control is available per DQ/DQS group. May 2011 Altera Corporation (Note 1), (2) OE Register PRN Register PRN D ...

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... To ensure device reliability and proper operation when interfacing with a 3.3-V I/O system using Stratix V devices, do not violate the absolute maximum ratings of the devices. Altera recommends performing IBIS or SPICE simulations to determine that the overshoot and undershoot voltages are within the specifications. When using a Stratix V device as a transmitter, you can use slow slew rate and series termination to limit overshoot and undershoot at the I/O pins ...

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... The 3.3-V LVTTL and 3.3-V LVCMOS I/O standards are supported using V (2) The current strength is represented by the driver impedance value (). Only R (3) Pending silicon characterization. 1 Altera recommends performing IBIS or SPICE simulations to determine the best current strength setting for your specific application. May 2011 Altera Corporation I ...

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... Altera recommends performing IBIS or SPICE simulations to determine the best slew rate setting for your specific application. I/O Delay The following sections describe programmable IOE delay and programmable output buffer delay ...

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... A higher V smaller V swing reduces power consumption. The Quartus II software allows four OD settings for programmable V medium low medium high, and 3 is high. May 2011 Altera Corporation level. CCIO . The programmable V OD swing improves voltage margins at the receiver end control— ...

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... Stratix (2) Altera recommends that you use an external clamping diode on the I/O pins when the input signal is 3 3.3 V. (3) Each I/O bank of a Stratix V device has its own VCCIO pins and supports only one V standard is not supported when ...

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... Stratix V devices support driver-impedance matching to provide the I/O driver with controlled output impedance that closely matches the impedance of the transmission line result, you can significantly reduce reflections. Stratix V devices support R OCT for single-ended I/O standards (refer to S May 2011 Altera Corporation S OCT. T OCT and the programmable current strength for the S supply with the I/O bank where it is located ...

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... Figure 5–4 is the intrinsic impedance of the transistors. Calibration OCT with Calibration Stratix V Driver Series Termination V CCIO Ω GND Chapter 5: I/O Features in Stratix V Devices OCT Support and I/O Termination Schemes Receiving Device OCT S OCT setting ( OCT S Receiving Device May 2011 Altera Corporation ...

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... Differential SSTL-18 Class II Differential SSTL15 Class I Differential SSTL15 Class II Differential HSTL 1.8 Class I Differential HSTL 1.8 Class II Differential HSTL 1.5 Class I Differential HSTL 1.5 Class II Differential HSTL 1.2 Class I May 2011 Altera Corporation Output Termination Uncalibrated R Calibrated R OCT s s OCT Setting, R ( ...

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... OCT with T Figure 5–5 shows of the bank must match CCIO Stratix V OCT V CCIO 100 100 Receiver GND May 2011 Altera Corporation ...

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... Altera recommends using the new I/O standards for the DDR3 memory interface with dynamic OCT schemes. These I/O standards save board space by reducing the number of external termination resistors used ...

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... Bank 3C Bank 3D Bank 3E Bank 4E Bank 4D Bank 4C Chapter 5: I/O Features in Stratix V Devices OCT Calibration OCT is supported in all I/O D and V is set to 2.5 V. CCPD Receiver 100 Ω on all I/O pins with T RZQ pin Bank 7B Bank 7A Bank 4B Bank 4A RZQ pin May 2011 Altera Corporation ...

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... Figure 5–9. Example of Calibrating Multiple I/O Banks with One Shared OCT Calibration Block—Preliminary Bank 8A Bank 8B Bank 3A Bank 3B May 2011 Altera Corporation as the I/O bank that contains the block. CCIO CCIO Figure 5–9 shows a group of I/O banks that has the same V ...

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... When ENOCT = 0, each signal enables the OCT serializer for the corresponding OCT calibration block. When ENAOCT = 1, each signal enables OCT calibration for the corresponding OCT calibration block. Serial-to-parallel load enable per I/O bank. Clear user. OCT Calibration May 2011 Altera Corporation ...

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... calibration block number), you must assert ENAOCT one cycle before asserting ENASER[N]. Also, nCLRUSR must be set to low for one OCTUSRCLK cycle before the ENASER[N] signal is asserted. Assert the ENASER[N] signals for 1000 OCTUSRCLK cycles to perform R cycle after the last ENASER is deasserted. May 2011 Altera Corporation CB8 ENAOCT, nCLRUSR, S2PENA_6C Stratix V ...

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... S2PENA is asserted for parallel codes transfer. Stratix V Device Handbook Volume 2: Device Interfaces and Integration OCT and 16-bit R OCT) from each OCT calibration block to the S T Calibration Phase 1000 OCTUSRCLK Cycles Chapter 5: I/O Features in Stratix V Devices OCT Calibration Figure 5–11). 32 OCTUSRCLK Cycles t s2p (1) May 2011 Altera Corporation ...