DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 457

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

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SV52005-1.2
10GBASE-R
Stratix V Device Handbook Volume 3: Transceivers
May 2011
May 2011
SV52005-1.2
f
f
This chapter provides the transceiver channel datapath, clocking guidelines, channel
placement guidelines, and a brief description of protocol features supported in each
transceiver configuration for Stratix
Stratix V devices have dedicated transceiver physical coding sublayer (PCS) and
physical medium attachment (PMA) circuitry to support the following
communication protocols:
■
■
■
■
■
For a complete list of serial protocols supported by Stratix V devices, refer to the
Upcoming Stratix V Device Features
Use this chapter along with the
your intended protocol links in Stratix V devices.
Table 4–1
for each supported transceiver configuration.
Table 4–1. Quartus II PHY IP Core Names
This section describes 10GBASE-R link implementation using Stratix V transceivers. It
provides the transceiver channel datapath, clocking, and channel placement
guidelines when configured in a 10GBASE-R configuration.
10GBASE-R is a specific physical layer implementation of the 10 Gigabit Ethernet link
defined in clause 49 of the IEEE 802.3-2008 specification. As shown in
10GBASE-R PHY uses the XGMII interface to connect to the IEEE802.3 media access
control (MAC) and reconciliation sublayer (RS). The IEEE 802.3-2008 specification
requires each 10GBASE-R link to support a 10 Gbps data rate at the XGMII interface
and a 10.3125 Gbps serial line rate with 64B/66B encoding.
“10GBASE-R”
“Interlaken” on page 4–8
“PCI Express (PCIe)—Gen1 and Gen2” on page 4–15
“GIGE” on page 4–30
“XAUI” on page 4–37
Transceiver Configuration
PCI Express
lists the Quartus
10GBASE-R
Interlaken
XAUI
®
4. Transceiver Protocol Configurations in
(PCIe
®
®
)
II PHY IP Core instance names that you must instantiate
Altera Transceiver PHY IP Core User Guide
document.
®
V devices.
PCI Express PHY (PIPE)
Quartus II PHY IP Core
10GBASE-R PHY
Interlaken PCS
XAUI PHY
Stratix V Devices
Figure
to implement
4–1, the
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