DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 405

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
10G PCS Architecture
Figure 1–29. 10G PCS Datapath for Stratix V Devices
Note to
(1) Not all the blocks shown in the 10G PCS datapath are available in every configuration.
May 2011 Altera Corporation
Figure
Fabric
FPGA
tx_clkout
rx_clkout
1–29:
(From Dedicated Input Reference Clock Pin)
f
f
Input Reference Clock
CMU PLL
The functional blocks in the 10G PCS hard macro provide status and control signals to
the FPGA fabric. For the signal names, refer to the
Guide.
The clocking schemes and placement restrictions for the different datapath
configurations are described in the
Devices
Figure 1–29
Serial Clock
and
Transceiver Custom Configurations in Stratix V Devices
shows the 10G PCS datapath.
Central/ Local Clock Divider
Monitor
BER
Parallel and Serial Clocks
(Note 1)
Clock Divider
Transceiver Protocol Configurations in Stratix V
Stratix V Device Handbook Volume 3: Transceivers
Altera Transceiver PHY IP Core User
Transmitter 10G PCS
Receiver 10G PCS
chapters.
Transmitter PMA
Receiver PMA
Parallel Clock
Serial Clock
Parallel and Serial Clocks
1–33