DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 104

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–10
Figure 2–8. Timing Waveform for Read-Write Operations (Single-Port Mode)
Table 2–7. M20K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 1 of 2)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
16K x 1
8K x 2
Read Port
Simple Dual-Port Mode
16K x 1
q_a (asynch)
v
v
address
byteena
data_a
clk_a
Figure 2–8
mode with unregistered outputs. Registering the RAM outputs delay the q output by
one clock cycle.
wren
All embedded memory blocks support simple dual-port mode. Simple dual-port
mode allows you to perform one-read and one-write operation to different locations
at the same time. The write operation happens on port A; the read operation happens
on port B.
Figure 2–9. Simple Dual-Port Memory for Stratix V Devices
Note to
(1) Simple dual-port RAM supports input/output clock mode and read/write clock mode.
Simple dual-port mode supports different read and write data widths (mixed-width
support).
dual-port mode. MLABs do not have native support for mixed-width operations. The
Quartus II software implements mixed-width memories in MLABs with more than
one MLAB.
rden
8K x 2
v
v
Figure
Table 2–7
Figure 2–9
shows timing waveforms for read and write operations in single-port
2–9:
4K x 4
A123
v
v
A123
lists the mixed width configurations for M20K blocks in simple
shows a simple dual-port configuration.
4K x 5
B456
—
—
A0
B456
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
2K x 8
C789
v
v
Write Port
C789
11
DDDD
2K x 10
—
—
DDDD
rd_addressstall
rdaddress[ ]
ecc_status
rdclocken
Chapter 2: Memory Blocks in Stratix V Devices
1K x 16
A1
EEEE
rdclock
v
v
(Note 1)
rden
aclr
q[ ]
EEEE
FFFF
1K x 20
—
—
May 2011 Altera Corporation
FFFF
512 x 32
v
v
Memory Modes
512 x 40
—
—