DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 293

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Fast Passive Parallel Configuration
Figure 9–4. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
Notes to
(1) Use this timing waveform when the DCLK-to-DATA[] ratio is 1.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When
(3) After power-up, the Stratix V device holds nSTATUS low for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) For FPP ×16, use DATA[15..0]. For FPP ×8, use DATA[7..0]. DATA[31..0] are available as a user I/O pin after configuration. The state of this
(7) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONE is released high when the Stratix V
(8) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
May 2011 Altera Corporation
nCONFIG is pulled low, a reconfiguration cycle begins.
pin depends on the dual-purpose pin settings.
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization
and enter user mode.
Figure
FPP Configuration Timing
9–4:
1
CONF_DONE (4)
INIT_DONE
DATA[31..0]
nSTATUS (3)
nCONFIG
Figure 9–4
device as an external host. This waveform shows timing when the DCLK-to-DATA[]
ratio is 1.
When you enable the decompression or design security feature, the DCLK-to-DATA[]
ratio varies for FPP ×8, FPP ×16, and FPP ×32. For the respective DCLK-to-DATA[] ratio,
refer to
User I/O
DCLK
(6)
(8)
Table 9–6 on page
t
t
CF2CD
CFG
shows the timing waveform for FPP configuration when using a MAX II
t
CF2ST1
t
CF2ST0
t
t
CF2CK
ST2CK
Word 0 Word 1 Word 2 Word 3
t
STATUS
High-Z
t
CH
t
CLK
t
DSU
t
CL
t
DH
9–9.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Word n-2 Word n-1
(7)
Word n
t
CD2UM
(Note
1),
User Mode
User Mode
(5)
(2)
9–13