DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 228

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

6–14
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Receiver Hardware Blocks
Figure 6–12
Figure 6–12. On-Chip Differential I/O Termination
The differential receiver has the following hardware blocks:
■
■
■
■
DPA Block
The DPA block takes in high-speed serial data from the differential input buffer and
selects one of the eight phases generated by the fractional PLLs to sample the data.
The DPA chooses a phase closest to the phase of the serial data. The maximum phase
offset between the received data and the selected phase is 1/8 UI, which is the
maximum quantization error of the DPA. The eight phases of the clock are equally
divided, offering a 45
Figure 6–13
incoming serial data.
Figure 6–13. DPA Clock Phase to Serial Data Timing Relationship
Note to
(1) T
“DPA Block” on page 6–14
“Synchronizer” on page 6–15
“Data Realignment Block (Bit Slip)” on page 6–15
“Deserializer” on page 6–17
VCO
Figure
is defined as the PLL serial clock period.
rx_in
6–13:
135˚
180˚
225˚
270˚
315˚
shows device on-chip termination.
shows the possible phase relationships between the DPA clocks and the
45˚
90˚
0˚
0.125T
Transmitter
°
LVDS
D0
resolution.
vco
Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
D1
T
D2
vco
D3
R
D
D4
(Note 1)
Dn
May 2011 Altera Corporation
Differential Receiver