DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 282

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–2
Configuration Features
Power-On Reset Circuit and Configuration Pins Power Supply
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
POR Delay Specification
f
Stratix V devices offer decompression, design security, and remote system upgrade
features. Stratix V devices can receive a compressed configuration bitstream and
decompress this data in real-time, reducing storage requirements and configuration
time. Design security using configuration bitstream encryption is available in
Stratix V devices, which protects your designs. You can make real-time system
upgrades of your Stratix V designs from remote locations with the remote system
upgrade feature.
Table 9–1
Table 9–1. Configuration Features for Stratix V Devices
The following sections describe the power-on reset (POR) circuit and the power
supply for the configuration pins.
POR delay is defined as the delay between the time when all the power supplies
monitored by the POR circuitry reach the minimum recommended operating voltage
to the time when the nSTATUS is released high and your device is ready to begin
configuration.
For more information about the POR delay, refer to the
Reset in Stratix V Devices
Table 9–2
Table 9–2. Fast and Standard POR Delay Specification
FPP (×8, ×16, ×32)
AS (×1, ×4)
PS
JTAG
Note to
(1) In these configuration schemes, the host system must accommodate a different DCLK-to-DATA[] ratio. For
Fast
Standard
Note to
(1) You can select the POR delay based on the MSEL settings as described in
Configuration Scheme
more information, refer to
Table
Table
lists which configuration features you can use in each configuration scheme.
lists the fast and standard POR delay specification.
POR Delay
9–1:
9–2:
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
“Fast Passive Parallel Configuration” on page
chapter.
Decompression
v
v
v
—
(1)
Minimum
100 ms
4 ms
Design Security
(Note 1)
v
v
v
—
(1)
Hot Socketing and Power-On
9–9.
Table 9–4 on page
May 2011 Altera Corporation
Remote System
Maximum
300 ms
Configuration Features
12 ms
9–7.
Upgrade
—
v
—
—