DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 259

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 7: External Memory Interfaces in Stratix V Devices
Stratix V External Memory Interface Features
May 2011 Altera Corporation
Phase Offset Control
f
f
1
The seven-bit DQS delay settings from the DLL vary with PVT to implement the
phase-shift delay.
For the frequency range of each mode, refer to the
Stratix V Devices
For a 0° shift, the DQS/CQ signal bypasses both the DLL and DQS logic blocks. The
Quartus II software automatically sets the DQ input delay chains, so that the skew
between the DQ and DQS/CQ pin at the DQ IOE registers is negligible if a 0° shift is
implemented. You can feed the DQS delay settings to the DQS logic block and logic
array.
The shifted DQS/CQ signal goes to the DQS bus to clock the IOE input registers of the
DQ pins. The signal can also go into the logic array for resynchronization if you are
not using IOE resynchronization registers. The shifted CQn signal can only go to the
negative-edge input register in the DQ IOE and is only used for QDR II+ and
QDR II SRAM interfaces.
Each DLL has two phase-offset modules and can provide two separate DQS delay
settings with independent offsets, one for the top and bottom I/O bank and one for
the left and right I/O bank, so you can fine-tune the DQS phase-shift settings between
two different sides of the device. Even though you have independent phase offset
control, the frequency of the interface using the same DLL must be the same. Use the
phase offset control module for making small shifts to the input signal and use the
DQS phase-shift circuitry for larger signal shifts. For example, if the DLL only offers a
multiple of a 45° phase shift, but your interface must have a 97.5° phase shift on the
DQS signal, you can use two delay chains in the DQS logic blocks to give you a
90° phase shift and use the phase offset control feature to implement the extra
7.5° phase shift.
You can use either a static phase offset or a dynamic phase offset to implement the
additional phase shift. The available additional phase shift is implemented in
2’s complement in Gray-code between settings –128 to +127. An additional bit
indicates whether the setting has a positive or negative value. The settings are linear,
each phase offset setting adds a specified delay amount. The DQS phase shift is the
sum of the DLL delay settings and the user-selected phase offset settings whose top
setting is 128, so the actual physical offset setting range is 128 subtracted by the DQS
delay settings from the DLL.
When using this feature, you must monitor the DQS delay settings to know how
many offsets you can add and subtract in the system. The DQS delay settings output
by the DLL are also Gray coded.
For example, if the DLL determines that DQS delay settings of 28 is required to
achieve a 30° phase shift, you can subtract up to 28 phase offset settings and you can
add up to 99 phase offset settings to achieve the optimal delay that you require.
For more information about the value for each step and the specified delay amounts
for the phase offset setting, refer to the
Devices
chapter.
chapter.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
DC and Switching Characteristics for Stratix V
DC and Switching Characteristics for
7–15