DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 307

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Active Serial Configuration (Serial Configuration Devices)
May 2011 Altera Corporation
1
Figure 9–14
the AS interface.
Figure 9–14. Connection Setup for Programming the EPCQ Device Using the AS Interface
Notes to
(1) Using the AS header, the programmer transmits the operation commands and the configuration bits to the EPCQ
(2) Connect the pull-up resistors to V
(3) Power up the USB-ByteBlaster, ByteBlaster II, or EthernetBlaster cable's V
(4) The MSEL pin settings vary for different configuration voltage standards and POR delays. To connect the MSEL, refer
(5) You can use the CLKUSR pin to supply the external clock source to drive the DCLK during configuration. The
During EPCS and EPCQ programming, the download cable disables the device access
to the AS interface by driving the nCE pin high. The nCONFIG line is also pulled low
to hold the Stratix V device in reset stage. After programming completes, the
download cable releases nCE and nCONFIG, allowing the pull-down and pull-up
resistors to drive the pin to GND and V
During EPCQ programming using the download cable, DATA0 carries the
programming data, operation command, and address information from the download
cable into the EPCQ device. During EPCQ verification using the download cable,
DATA1 carries the programming data back to the download cable.
(Note 1)
device serially on DATA0.This is equivalent to the programming operation for the EPCS device as shown in
Figure
to
maximum frequency specification is 100 MHz.
Table 9–4 on page
Figure
9–14.
shows the connection setup when programming the EPCQ device using
9–14:
EPCQ Device
9–7.
DATA0
DATA1
DATA2
DATA3
DCLK
nCS
V
CCPGM (2)
10 kΩ 10 kΩ
CCPGM
and V
USB-Blaster or ByteBlaser II
V
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
CCPGM (2)
10-Pin Male Header
CCPD
Pin 1
(AS Mode)
CCPGM
at a 3.0-V supply.
10 kΩ
V
V
CCPGM (2)
10 kΩ
CCPGM (3)
, respectively.
AS_DATA0/ASDO
AS_DATA1
AS_DATA2
AS_DATA3
DCLK
nCSO
CONF_DONE
nSTATUS
nCONFIG
nCE
Stratix V Device
CC(TRGT)
MSEL[4..0]
CLKUSR
nCEO
with V
CCPGM
(4)
(5)
N.C.
.
9–27