DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 270

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–26
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
I/O Configuration Block and DQS Configuration Block
Each DQS logic block contains a delay chain after the dqsbusout output and another
delay chain before the dqsenable input.
DQS input path.
Figure 7–16. Delay Chains in the DQS Input Path
The I/O configuration block and the DQS configuration block are shift registers that
you can use to dynamically change the settings of various device configuration bits.
The shift registers power-up low. Every I/O pin contains one I/O configuration
register while every DQS pin contains one DQS configuration block in addition to the
I/O configuration register.
DQS configuration block circuitry.
Figure 7–17. I/O Configuration Block and DQS Configuration Block
rankselectwrite
DQS
rankselectread
dqsenabledelaysetting
update
datain
ena
clk
Figure 7–17
bit0
dqsenable
dqsin
Enable
Control
Enable
delay
DQS
chain
DQS
bit1
T11
shows the I/O configuration block and the
bit2
Figure 7–16
Chapter 7: External Memory Interfaces in Stratix V Devices
DQS delay
chain
shows the delay chains in the
Stratix V External Memory Interface Features
dqsbusoutdelaysetting
delay
chain
T4
MSB
May 2011 Altera Corporation
dqsbusout
dataout