DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 392

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–20
Table 1–4. FPGA Fabric-Transceiver Interface Width and Transceiver PMA-PCS Widths for Stratix V Devices
Stratix V Device Handbook Volume 3: Transceivers
PMA-PCS interface widths
FPGA fabric-transceiver interface width
Supported configurations
Data rate range in a custom configuration
Receiver Standard PCS Datapath
Name
Table 1–4
transceiver PMA-PCS widths (serialization factor) allowed in single-width and
double-width configurations.
This section describes the receiver channel datapath architecture. The sub-blocks in
the receiver datapath are described in order from the word aligner to the receiver
phase compensation FIFO buffer at the FPGA fabric-transceiver interface.
on page 1–18
The receiver channel standard PCS datapath consists of the following blocks:
■
■
■
■
■
■
The receiver datapath is flexible and allows multiple modes, depending on the
selected configuration.
Word Aligner
Because the data is serialized before transmission and then deserialized at the
receiver, the data loses the word boundary of the upstream transmitter after
deserialization. The word aligner receives parallel data from the deserializer and
restores the word boundary based on a pre-defined alignment pattern that must be
received during link synchronization.
Serial protocols such as PCIe specify a standard word alignment pattern. For
proprietary protocols, the transceiver architecture allows you to select a custom word
alignment pattern specific to your implementation.
“Word Aligner” on page 1–20
“Rate Match (Clock Rate Compensation) FIFO” on page 1–24
“8B/10B Decoder” on page 1–25
“Byte Deserializer” on page 1–26
“Byte Ordering Block” on page 1–27
“Receiver Phase Compensation FIFO” on page 1–28
lists the FPGA fabric-transceiver interface widths (channel width) and
shows the receiver channel datapath.
8 and 10 bit
8 and 10 bit
16 and 20 bit
■
■
■
0.6 to 3.75 Gbps
PCIe Gen1 and Gen2
XAUI
Custom single-width
Single-Width
(available in PCIe configuration only)
Chapter 1: Transceiver Architecture in Stratix V Devices
16 and 20 bit
16 and 20 bit
32 and 40 bit
Custom double-width
1.0 to 8.5 Gbps
Double-Width
May 2011 Altera Corporation
Standard PCS Architecture
Figure 1–16