DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 376

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–4
Stratix V Device Handbook Volume 3: Transceivers
f
Figure 1–4. Number of Channels in Each Transceiver Bank for 5SGXA3 and 5SGXA4 Devices
Figure 1–5. Number of Channels in Each Transceiver Bank for 5SGSB7 and 5SGSB8 Devices
For more information about device options, refer to the
Overview
Stratix V GX and GS transceivers are structured into full-duplex (transmitter and
receiver) six-channel groups called transceiver blocks. The transmitter and receiver
can operate separately. Each channel’s transmitter and receiver is made up of a PMA
and a PCS section
phase-locked loop (PLL), serializer, and deserializer. The PCS section has a choice of
either standard PCS or 10G PCS.
chapter.
(Figure
GXB_L2
GXB_L1
GXB_L0
GXB_L4
GXB_L3
GXB_L2
GXB_L1
GXB_L0
1–6). The PMA contains the transceiver buffer, channel
6 Ch
6 Ch
6 Ch
Number of Channels Per Bank
Transceiver Bank Names
3 Ch
6 Ch
6 Ch
6 Ch
6 Ch
Devices Available
5SGXA3 KF35
5SGXA3 KF40
5SGXA4 KF35
5SGXA4 KF40
5SGXA3 HF29
5SGXA3 HF35
5SGXA4 HF29
5SGXA4 HF35
Number of Channels Per Bank
Transceiver Bank Names
Devices Available
Chapter 1: Transceiver Architecture in Stratix V Devices
5SGSB7
5SGSB7
5SGSB8
5SGSB8
6 Ch
6 Ch
6 Ch
RF40
IF45
RF40
IF45
Stratix V Device Family
GXB_R2
GXB_R1
GXB_R0
May 2011 Altera Corporation