DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 107

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: Memory Blocks in Stratix V Devices
Memory Modes
Table 2–8. M20K Block Mixed-Width Configurations (True Dual-Port Mode)
May 2011 Altera Corporation
16K x 1
8K x 2
4K x 4
4K x 5
2K x 8
2K x 10
1K x 16
1K x 20
Port A
16K x 1
v
v
v
—
v
—
v
—
Table 2–8
dual-port mode.
In true dual-port mode, M20K memory blocks support separate write-enable and
read-enable signals. You can save power by keeping the read-enable signal low
(inactive) when not reading. Read-during-write operations to the same address can
either output “new data” at that location or “old data”. To choose the desired
behavior, set the read-during-write behavior to either new data or old data in the
RAM MegaWizard Plug-In Manager in the Quartus II software. For more information,
refer to
In true dual-port mode, you can access any memory location at any time from either
port. If you are accessing the same memory location from both ports, you must avoid
possible write conflicts. A write conflict happens if you are writing to the same
address location from both ports at the same time. This results in unknown data being
stored to that address location. No conflict resolution circuitry is built into the
Stratix V embedded memory blocks. You must resolve address conflicts external to
the RAM block.
8K x 2
v
v
v
v
v
“Read-During-Write Behavior” on page
—
—
—
lists the possible M20K block mixed-port width configurations in true
4K x 4
v
v
v
v
v
—
—
—
4K x 5
—
—
—
v
—
v
—
v
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Port B
2K x 8
v
v
v
v
v
—
—
—
2–17.
2K x 10
v
v
v
—
—
—
—
—
1K x 16
v
v
v
—
v
—
v
—
1K x 20
v
v
v
—
—
—
—
—
2–13