DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 386

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–14
Figure 1–14. Clock Dividers
Stratix V Device Handbook Volume 3: Transceivers
(From the ×6 or ×N Clock Lines)
(From the ×6 or ×N Clock Lines)
(From the ×1 Clock Lines)
(From the ×1 Clock Lines)
Parallel and Serial Clocks
Parallel and Serial Clocks
Input Reference Clock
Input Reference Clock
To the ×1 Clock Lines
Serial Clock
Serial Clock
Clock Divider
Each transmitter channel has a clock divider called a local clock divider. Some clock
dividers have special access and are called a central clock divider.
the two types of clock dividers. The central clock dividers are located in Channels 1
and 4 of the transceiver block channels numbered 0-5. The combination of the CMU
through the clock divider generates the parallel and serial clock sources for the
transmitter and optionally in the receiver PCS. The central clock divider can feed the
clock lines used to bond channels.
Central Clock Divider
Local Clock Divider
CMU PLL
CMU PLL
Divider
Divider
Clock
Clock
/4, /5
/4, /5
Parallel and Serial Clocks
Serial Clock
Chapter 1: Transceiver Architecture in Stratix V Devices
Ch1 RX
Ch0 RX
Ch1 TX
Ch0 TX
May 2011 Altera Corporation
Parallel and Serial Clocks
(To the ×6 and ×N Clock Lines)
To the Transmitter
and Receiver
To the Transmitter
and Receiver
Figure 1–14
PMA Architecture
shows