DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 492

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

4–36
Stratix V Device Handbook Volume 3: Transceivers
Table 4–7
Table 4–7. Transceiver Datapath Clock Frequencies in GIGE Mode
Transceiver Channel Placement Guidelines
There are no specific placement constraints when placing a GIGE transceiver channels
in a transceiver bank. Up to five GIGE channels may be placed on channels 0, 2, 3, 5,
and either channel 1 or channel 4 when using the CMU PLL; Up to six GIGE channels
may be placed anywhere on one of the six transceiver channels per bank when using
the ATX PLL.
the CMU PLL or the ATX PLL to drive the GIGE link. If a CMU PLL is implemented,
channel 1 or channel 4 in a transceiver bank generates the transmitter serial clock to
drive the ×1 clock lines for up to five GIGE channels per transceiver bank. If an ATX
PLL is implemented, the ATX PLL generates the transmitter serial clock to drive the
×1 clock lines for up to six GIGE channels per transceiver bank.
Functional
Mode
GIGE
lists the transceiver datapath clock frequencies in GIGE functional mode.
Figure 4–27
Data Rate
1.25 Gbps
Line
High-Speed Serial
shows the allowed channel placement when using either
Clock Frequency
Half-Rate
625 MHz
Chapter 4: Transceiver Protocol Configurations in Stratix V Devices
Fabric-Transceiver
Interface Width
1-bit control
8-bit data,
FPGA
FPGA Fabric-Transceiver
May 2011 Altera Corporation
Interface Clock
Frequency
125 MHz
GIGE