DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 520

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

5–18
Stratix V Device Handbook Volume 3: Transceivers
f
Figure 5–16
PMA-PCS interface width. The blocks shown as “Disabled” are not used, but incur
latency. The blocks shown as “Bypassed” are not used and do not incur any latency.
The maximum frequencies shown in
For more information about the maximum data rate for a certain speed grade, refer to
the
Figure 5–16. Standard PCS Low Latency 16-Bit PMA-PCS Interface Width
DC and Switching Characteristics for Stratix V Devices
Data Rate (Gbps)
Number of Bonded Channels
Word Aligner (Pattern Length)
Rate Match FIFO
8B/10B Encoder/Decoder
Byte Serializer/Deserializer
Data Rate (Gbps)
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
shows the available options for the standard PCS low latency 16-bit
Chapter 5: Transceiver Custom Configurations in Stratix V Devices
Figure 5–16
Standard PCS Custom and Low Latency Configurations
are for the fastest devices.
Bypassed Bypassed
Disabled Enabled
265.625
16-Bit
62.5-
4.25
1.0-
Bypassed
Bypassed
Bypassed
Up to ×5
1.0-8.5
chapter.
265.625
31.25-
32-Bit
1.0-
8.5
May 2011 Altera Corporation