DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 412

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

1–40
Stratix V Device Handbook Volume 3: Transceivers
1
64B/66B Encoder
The 64B/66B encoder
specification as described in the IEEE 802.3-2008 clause-49.
The block contains two sub-blocks:
■
■
The 64B/66B encoder block
encodes the 64-bit data and 8-bit control characters to the 66-bit data block required by
the 10GBASE-R configuration. The transmit state machine in this block checks the
validity of the 64-bit data from the MAC layer and ensures proper block sequencing.
The 64B/66B encoder is only used in the 10GBASE-R configuration.
Figure 1–37. 64B/66B Encoder
Scrambler
Long sequences of zeros or ones and repetition of data patterns in the data stream can
cause interference with adjacent channels and electromagnetic interference (EMI).
Data scrambling reduces these effects.
The scrambler
■
■
64B/66B Encoder
Transmitter State Machine
Frame synchronous mode—used in the Interlaken configuration
Self synchronous mode—used in the 10GBASE-R configuration as specified in the
IEEE 802.3-2008 clause-49
From TX FIFO
(Figure
8-Bit Control
64-Bit Data
(Figure
1–38) operates in two modes:
(Figure
1–37) is designed for the 10GBASE-R protocol
1–37) receives data from the transmitter FIFO. It
64B/66B
TX State
Machine
Encoder
Chapter 1: Transceiver Architecture in Stratix V Devices
May 2011 Altera Corporation
Data Block to Scrambler
Encoded 66-Bit
10G PCS Architecture