DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 147

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Clock Networks in Stratix V Devices
May 2011 Altera Corporation
Clock Regions
Stratix V devices provide the following types of clock regions:
■
■
■
Entire Device Clock Region
To form the entire device clock region, a source (not necessarily a clock signal) drives a
GCLK network that can be routed through the entire device. This clock region has the
maximum delay when compared with other clock regions, but allows the signal to
reach every destination within the device. This is a good option for routing global
reset and clear signals or routing clocks throughout the device.
Regional Clock Region
To form a RCLK region, a source drives a single quadrant of the device. This clock
region provides the lowest skew within a quadrant and is a good option if all the
destinations are within a single device quadrant.
Dual-Regional Clock Region
To form a dual-regional clock region, a single source (a clock pin or PLL output)
generates a dual-regional clock by driving two RCLK networks (one from each
quadrant). This technique allows destinations across two device quadrants to use the
same low-skew clock. The routing of this signal on an entire side has approximately
the same delay as a RCLK region. Internal logic can also drive a dual-regional clock
network. Corner PLL outputs only span one quadrant, they cannot generate a
dual-regional clock network.
Figure 4–8
Figure 4–8. Dual-Regional Clock Region for Stratix V Devices
“Entire Device Clock Region” on page 4–7
“Regional Clock Region” on page 4–7
“Dual-Regional Clock Region” on page 4–7
shows the dual-regional clock region.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Clock pins or PLL outputs
can drive half of the device to
create dual-regional clocking
regions for improved
interface timing.
4–7