DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 53

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
Figure 2–2. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to or Higher Than
1.25 Gbps
May 2011 Altera Corporation
0.35
8.5
25
0.1
F1
Figure 2–2
tolerance specification for a data rate equal to or higher than 1.25 Gbps.
lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a data rate
equal to or higher than 1.25 Gbps.
Table 2–28. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to or Higher
than 1.25 Gbps—Preliminary
F2
shows the LVDS soft-clock data recovery (CDR)/DPA sinusoidal jitter
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
F1
F2
F3
F4
Jitter Frequency (Hz)
Jitter Frequency (Hz)
50,000,000
F3
1,493,000
10,000
17,565
Stratix V Device Handbook Volume 1: Overview and Datasheet
Sinusoidal Jitter (UI)
F4
25.000
25.000
0.350
0.350
Table 2–28
2–25