DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 415

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
PLL Sharing
PLL Sharing
Document Revision History
Table 1–17. Document Revision History
May 2011 Altera Corporation
May 2011
December 2010
December 2010
July 2010
April 2010
Date
f
Version
■
The Stratix V transceivers support various bonded and non-bonded transceiver
clocking configurations. For more information, refer to the
Stratix V Devices
Two different protocol configurations in a Quartus II design can be merged to share
the same CMU PLL resources. The two configurations must fit in the same transceiver
bank and the input refclk and PLL output frequencies must be the same.
Table 1–17
1.4
1.3
1.2
1.1
1.0
Non-bonded channel configurations—the parallel clock in each channel are
generated independently by its local clock divider, resulting in higher
channel-to-channel clock skew.
The transmitter phase compensation FIFO in each non-bonded channel has its
own pointers and control logic that can result in unequal latency in the transmitter
phase compensation FIFO of each channel. The higher transceiver clock skew and
unequal latency in the transmitter phase compensation FIFO in each channel can
result in higher channel-to-channel skew.
■
■
■
■
■
■
■
■
■
■
■
■
Initial release in the Stratix V Device Handbook.
Initial release for EAP.
Chapter moved to Volume 3.
Minor text edits.
Updated Figure 1–16.
Minor graphic edits
Updated to include Quartus II version 10.1 information.
Reorganized chapter information.
Added the “Channel PLL Used as a CMU PLL (Transmitter PLL)” and “Auxiliary Transmit
(ATX) PLL Architecture” sections.
Added Figure 1–11.
Updated the “Bonded Configuration” section.
Updated Figure 1–2, Figure 1–3, Figure 1–4, Figure 1–5, Figure 1–7, Figure 1–8,
Figure 1–14, Figure 1–16, and Figure 1–29.
Reversed Rx directional flow in Figure 1–8, Figure 1–18, Figure 1–19, Figure 1–20,
Figure 1–21, and Figure 1–22.
Minor text edits.
lists the revision history for this chapter.
chapter.
Changes
Stratix V Device Handbook Volume 3: Transceivers
Transceiver Clocking in
1–43