DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 286

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

9–6
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
User Mode
1
CLKUSR provides you with the flexibility to synchronize initialization of multiple
devices or to delay initialization. Supplying a clock on the CLKUSR pin during
initialization does not affect configuration. After CONF_DONE goes high, CLKUSR or DCLK
is enabled after the time specified by t
devices require a minimum number of clock cycles to initialize properly and enter
user mode as specified by the t
The Stratix V device enters user mode when the initialization is complete. You can
monitor the end of the initialization stage by enabling the optional INIT_DONE pin. If
enabled, the low-to-high transition of INIT_DONE indicates the device has completed
initialization and entered user mode. In this mode, your design is executed. The user
I/O pins no longer have weak pull-up resistors and function as assigned in your
design.
At any time during the configuration stage or user mode operation, you can initiate a
reconfiguration by setting a low pulse on the nCONFIG pin. The pulse must meet the
minimum t
CONF_DONE pins are pulled low and all I/O pins are tri-stated. Configuration begins
when the nCONFIG and nSTATUS pins return to a logic-high level.
CFG
low-pulse width. When nCONFIG is pulled low, the nSTATUS and
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
CD2UMC
CD2CU
parameter.
. When this time period elapses, Stratix V
May 2011 Altera Corporation
Configuration Sequence