DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 264

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–20
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Leveling Circuitry
DDR3 SDRAM unbuffered modules use a fly-by clock distribution topology for better
signal integrity. This means that the CK/CK# signals arrive at each DDR3 SDRAM
device in the module at different times. The difference in arrival time between the first
DDR3 SDRAM device and the last device on the module can be as long as 1.6 ns.
Figure 7–9
Figure 7–9. DDR3 SDRAM Unbuffered Module Clock Topology
Because the data and read strobe signals are still point-to-point, take special care to
ensure that the timing relationship between the CK/CK# and DQS signals (tDQSS,
tDSS, and tDSH) during a write is met at every device on the modules. In a similar way,
read data coming back into the FPGA from the memory is also staggered.
Stratix V FPGAs have leveling circuitry to address these two situations. There is one
leveling circuit per I/O sub-bank (for example, I/O sub-bank 1A, 1B, and 1C each has
one leveling circuitry). These delay chains are PVT-compensated by the same DQS
delay settings as the DLL and DQS delay chains.
The DLL uses eight delay chains, such that each delay chain generates a 45° delay. The
generated clock phases are distributed to every DQS logic block that is available in the
I/O sub-bank. The delay chain taps then feed a multiplexer controlled by the UniPHY
megafunction to select which clock phases are to be used for that x4 or x 8 DQS group.
Each group can use a different tap output from the read-leveling and write-leveling
delay chains to compensate for the different CK/CK# delay going into each device on
the module.
DQS/DQ
shows the clock topology in DDR3 SDRAM unbuffered modules.
DQS/DQ
DQS/DQ
DQS/DQ
CK/CK#
Chapter 7: External Memory Interfaces in Stratix V Devices
DQS/DQ
Stratix V External Memory Interface Features
DQS/DQ
DQS/DQ
May 2011 Altera Corporation
Stratix V Device
DQS/DQ