DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 341

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 10: SEU Mitigation in Stratix V Devices
User Mode Error Detection and Correction
May 2011 Altera Corporation
1
You can also read the error bit location through the JTAG and the core interface.
Before the error detection circuitry detects the next error in another frame, you must
shift erroneous bits out from the error message register (EMR) with either the JTAG
instruction, SHIFT_EDERROR_REG, or the core interface. The CRC circuitry continues to
run, and if an error is detected, you must decide whether to complete the
reconfiguration or to ignore the CRC error.
Table 10–1
Table 10–1. SHIFT_EDERROR_REG JTAG Instruction
Figure 10–1
Figure 10–1. Error Message Register
The type of error is identified in the first four bits of the EMR.
types represented in the EMR.
Table 10–2. Error Type in Error Message Register
For more information about the timing requirement to shift out error information
from the EMR, refer to
The error detection circuitry continues to calculate the 32-bit error detection CRC
value and 32-bit signatures for the next frame of data regardless of whether an error
has occurred in the current frame or not. You must monitor the CRC_ERROR signal and
take the appropriate actions if a CRC error occurs.
The error detection circuitry in Stratix V devices uses a 32-bit CRC-ANSI standard
(32-bit polynomial) as the CRC generator. The computed 32-bit CRC signature for
each frame is stored in the CRAM. The total storage size is 32 (number of bits
per frame) × the number of frames.
Bit 3
0
0
0
1
SHIFT_EDERROR_REG
JTAG Instruction
Bit 2
MSB
Error Type
0
0
0
1
Others
lists the instruction code for the SHIFT_EDERROR_REG JTAG instruction.
Syndrome
shows the content of the EMR.
32 bits
Bit 1
0
0
1
1
Frame Address
Bit 0
0
1
0
1
“Error Detection Timing” on page
16 bits
Instruction Code
No CRC error.
Location of a single-bit error is identified.
Location of a double-adjacent error is identified.
There is more than one error.
Reserved.
00 0001 0111
Double Word
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Location
10 bits
The JTAG instruction connects the EMR to the
JTAG pin in the error detection block between
the TDI and TDO pins.
Byte Offset
2 bits
Description
Bit Offset
10–8.
3 bits
Description
Table 10–2
Error Type
4 bits
lists the error
LSB
10–3