DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 243

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 6: High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
Differential Pin Placement Guidelines
Differential Pin Placement Guidelines
May 2011 Altera Corporation
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5. In the Set Input Delay window, set the appropriate values in the Input Delay
6. Click Run to incorporate these values in the TimeQuest Timing Analyzer.
7. Assign the appropriate delay for all the LVDS receiver input ports following these
If no input delay is set in the TimeQuest Timing Analyzer, the receiver
channel-to-channel skew (RCCS) defaults to zero. You can also directly set the input
delay in a synopsys design constraint file (.sdc) using the set_input_delay command.
For more information about .sdc commands and the TimeQuest Timing Analyzer,
refer to the
Development Software Handbook.
Example 6–1
Example 6–1. RSKM
Data Rate: 1 Gbps, Board channel-to-channel skew = 200 ps
For Stratix V devices:
TCCS = 100 ps (pending characterization)
SW = 300 ps (pending characterization)
TUI = 1000 ps
Total RCCS = TCCS + Board channel-to-channel skew= 100 ps + 200 ps
= 300 ps
RSKM= (TUI - SW - RCCS)/2
= (1000 ps — 300 ps — 300 ps)/2
= 200 ps
Because the RSKM > 0 ps, receiver non-DPA mode must work correctly.
You can also calculate RSKM using the steps described in
DPA-Enabled and DPA-Disabled Differential Channels” on page
To ensure proper high-speed operation, differential pin placement guidelines have
been established. The Quartus II compiler automatically checks that these guidelines
are followed and issues an error message if they are not met. This section is divided
into pin placement guidelines with and without DPA usage because DPA usage adds
some constraints on the placement of high-speed differential channels.
DPA-enabled differential channels refer to DPA mode or soft-CDR mode; DPA
disabled channels refer to non-DPA mode.
The information in the following sections is preliminary.
Options section and Delay value.
steps. If you have already assigned Input Delay and you need to add more delay
to that input port, use the Add Delay option in the Set Input Delay window.
Quartus II TimeQuest Timing Analyzer
shows the RSKM calculation.
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
chapter in volume 3 of the Quartus II
“Guidelines for
6–30.
6–29