DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 96

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–2
Table 2–1. Summary of Memory Features in Stratix V Devices (Part 2 of 2)
Table 2–2. Memory Capacity and Distribution in Stratix V Devices (Part 1 of 2)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Simple dual-port memory
True dual-port memory
Embedded shift register
ROM
FIFO buffer
Simple dual-port mixed width support
True dual-port mixed width support
Memory Initialization File (.mif)
Mixed-clock mode
Power-up condition
Register clears
Write/Read operation triggering
Same-port read-during-write
Mixed-port read-during-write
ECC support
Stratix V GX
Stratix V GT
Stratix V GS
Family
Feature
5SGXAB
5SGSD2
5SGSD3
5SGSD4
5SGSD5
5SGSD6
5SGSD8
5SGXA3
5SGXA4
5SGXA5
5SGXA7
5SGXA9
5SGXB5
5SGXB6
5SGTC5
5SGTC7
Device
Table 2–2
Stratix V device.
MLABs
11,736
15,850
17,960
11,270
11,736
11,000
13,280
3,776
5,880
8,020
9,250
8,020
2,450
4,536
6,264
8,630
lists the capacity and distribution of the embedded memory blocks in each
Outputs cleared if registered,
otherwise reads memory contents
Output registers
Write and Read—Rising clock edges
Outputs set to don’t care
Outputs set to old data or don’t care
Soft IP support using the Quartus
software
M20K Blocks
1,344
2,304
2,560
2,640
2,640
2,100
2,660
2,304
2,560
1,062
2,014
2,320
2,624
800
450
686
MLABs
v
—
v
v
v
—
—
v
v
Total Dedicated RAM Bits
(M20K Blocks Only) (Mb)
15.6
26.3
45.0
50.0
51.6
51.6
41.0
52.0
45.0
50.0
13.4
20.7
39.3
45.3
51.3
8.8

II
Chapter 2: Memory Blocks in Stratix V Devices
Outputs cleared
Output registers
Write and Read—Rising clock edges
Outputs set to new data
Outputs set to old data or don’t care
Built-in support in x32-wide simple
dual-port mode or soft IP support
using the Quartus II software
Total RAM Bits (Including
May 2011 Altera Corporation
M20K
v
v
v
v
v
v
v
v
v
LABs) (Mb)
17.9
29.8
49.9
57.2
61.2
62.5
46.7
58.8
49.9
57.2
10.3
16.2
24.6
44.6
52.0
59.4
Overview