DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 34

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DK-DEV-5SGXEA7/ES

Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Datasheets

Specifications of DK-DEV-5SGXEA7/ES

Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
2–6
Table 2–7. OCT Calibration Accuracy Specifications for Stratix V Devices—Preliminary (Part 2 of 2)
Stratix V Device Handbook Volume 1: Overview and Datasheet
20-, 30-,
40-,60-and
120- R
60- and 120-R
25- R
Note to
(1) OCT calibration accuracy is valid at the time of calibration only.
Table
S_left_shift
Symbol
T
2–7:
T
Internal parallel
termination with
calibration (20-, 30-
40-60-and 120-
setting)
Internal parallel
termination with
calibration (60- and
120- setting)
Internal left shift series
termination with
calibration (25- R
setting)
Description
S_left_shift
V
CCIO
V
CCIO
Conditions
V
1.5, 1.2 V
= 3.0, 2.5, 1.8,
CCIO
1.25 V
= 1.5, 1.35,
= 1.2
Chapter 2: DC and Switching Characteristics for Stratix V Devices
-10 to +40 -10 to +40 -10 to +40
-10 to +40 -10 to +40 -10 to +40
±15
C2
Calibration Accuracy
C3,I3
±15
May 2011 Altera Corporation
Electrical Characteristics
(Note 1)
C4,I4
±15
Unit
%
%
%

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