DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 354

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

11–4
Table 11–2. JTAG Instruction Supported by Stratix V Devices (Part 2 of 2)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
USERCODE
IDCODE
HIGHZ
CLAMP
PULSE_NCONFIG
CONFIG_IO
FACTORY
EXTEST_PULSE
EXTEST_TRAIN
Note to
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
JTAG Instruction
Table
(1)
(1)
11–2:
Only the five mandatory JTAG instructions (BYPASS, SAMPLE/PRELOAD, EXTEST,
EXTEST_PULSE, and EXTEST_TRAIN), the IDCODE optional instruction, and the FACTORY
private instruction are supported by the JTAG pins after power up and before
configuration. The FACTORY instruction must be issued before the device starts loading
the core configuration data to enable access to all other JTAG instructions. This
instruction also clears the device configuration data and AES volatile key.
The IDCODE instruction is the default instruction when the TAP controller is in the
reset state. Without loading any instructions, you can go to the SHIFT_DR state and
shift out the JTAG device ID.
Instruction Code
00 0000 0111
00 0000 0110
00 0000 1011
00 0000 1010
00 0000 0001
00 0000 1101
10 1000 0001
00 1000 1111
00 0100 1111
Selects the 32-bit USERCODE register and places it between the TDI
and TDO pins, allowing USERCODE to be serially shifted out of TDO.
Selects the IDCODE register and places it between the TDI and TDO
pins, allowing IDCODE to be serially shifted out of TDO. IDCODE is the
default instruction at power up and in the TAP RESET state.
Places the 1-bit bypass register between the TDI and TDO pins,
allowing the BST data to pass synchronously through selected devices
to adjacent devices during normal device operation while tri-stating all
of the I/O pins.
Places the 1-bit bypass register between the TDI and TDO pins,
allowing the BST data to pass synchronously through selected devices
to adjacent devices during normal device operation while holding I/O
pins to a state defined by the data in the boundary-scan register.
Emulates pulsing the nCONFIG pin low to trigger reconfiguration even
though the physical pin is unaffected.
Allows I/O reconfiguration through JTAG ports using IOCSR for JTAG
testing. This is executed after or during configurations. The nSTATUS
pin must go high before you can issue the CONFIG_IO instruction.
Enables access to all other JTAG instructions (other than BYPASS,
SAMPLE/PRELOAD, EXTEST, IDCODE, EXTEST_PULSE, and
EXTEST_TRAIN instructions, which are supported after power up).
This instruction also clears the device configuration data and advanced
encryption standard (AES) volatile key.
Enables board-level connectivity checking between the transmitters
and receivers that are AC coupled by generating three output
transitions:
■
■
■
Behaves the same as the EXTEST_PULSE instruction except that the
output continues to toggle on the TCK falling edge as long as the TAP
controller is in the RUN_TEST/IDLE state.
Driver drives data on the falling edge of TCK in the UPDATE_IR/DR
state.
Driver drives inverted data on the falling edge of TCK after entering
the RUN_TEST/IDLE state.
Driver drives data on the falling edge of TCK after leaving the
RUN_TEST/IDLE state.
Chapter 11: JTAG Boundary-Scan Testing in Stratix V Devices
Description
May 2011 Altera Corporation
BST Operation Control