DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 61

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Document Revision History
Table 2–36. Glossary (Part 4 of 4)
Document Revision History
Table 2–37. Document Revision History
May 2011 Altera Corporation
May 2011
December 2010
July 2010
Letter
W
V
X
Y
Z
Date
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
W
CM(DC)
ICM
ID
DIF(AC)
DIF(DC)
IH
IH(AC)
IH(DC)
IL
IL(AC)
IL(DC)
OCM
OD
SWING
X
OX
Subject
—
Version
Table 2–37
2.0
1.1
1.0
DC common mode input voltage.
Input common mode voltage—The common mode of the differential signal at the receiver.
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
AC differential input voltage—Minimum AC input differential voltage required for switching.
DC differential input voltage— Minimum DC input differential voltage required for switching.
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
High-level AC input voltage
High-level DC input voltage
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
Low-level AC input voltage
Low-level DC input voltage
Output common mode voltage—The common mode of the differential signal at the
transmitter.
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
Differential input voltage
Input differential cross point voltage
Output differential cross point voltage
High-speed I/O block—clock boost factor
■
■
■
■
■
■
■
Initial release.
Updated
Table
Updated the
Chapter moved to Volume 1.
Minor text edits.
Updated Table 1–2, Table 1–4, Table 1–19, and Table 1–23.
Converted chapter to the new template.
Minor text edits.
lists the revision history for this chapter.
2–24.
Table
“DQ Logic Block and Memory Output Clock Jitter Specifications”
2–4,
Table
2–18,
Table
Definitions
2–19,
Stratix V Device Handbook Volume 1: Overview and Datasheet
Changes
—
Table
2–21,
Table
2–22,
Table
2–23, and
title.
2–33