DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 283

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Power-On Reset Circuit and Configuration Pins Power Supply
May 2011 Altera Corporation
Power-On Reset Circuit
V
V
CCPGM
CCPD
f
f
1
Pin
Pin
The POR circuit keeps the entire system in reset mode until the power supply voltage
levels have stabilized on power-up. After power-up, the device does not release
nSTATUS until all the power supplies monitored by the POR circuitry are above the
device’s POR trip point. On power down, brown-out occurs if any of the power
supplies monitored by the POR circuitry drops below the threshold level of the
hot-socket circuitry.
For more information about which power supplies are monitored by the POR
circuitry, refer to the
Stratix V devices have a power supply, V
and dual-purpose pins. The supported configuration voltages are 1.8, 2.5, and 3.0 V.
Use the V
configuration outputs, dedicated configuration bidirectional pins, and the
dual-purpose pins that you use for configuration. The configuration input buffers do
not have to share power lines with the regular I/O buffer in Stratix V devices.
The operating voltage for the configuration input pin is independent of the I/O banks
power supply, V
require configuration voltage constraints on V
For more information about the configuration pins connections, refer to the
Device Family Pin Connection
Stratix V devices have a dedicated programming power supply, V
be connected to 3.0 V or 2.5 V to power the I/O pre-drivers and JTAG I/O pins (TCK,
TMS, TDI, TDO, and TRST).
V
powered up to 3.0 V. If the V
powered up to 2.5 V. This applies for all the banks containing the VCCPD and VCCIO
pins.
For more information about the configuration pins power supply, refer to
Configuration Pins” on page
CCPD
must be greater than or equal to V
CCPGM
CCIO
pin to power all dedicated configuration inputs, dedicated
Hot Socketing and Power-On Reset in Stratix V Devices
, during configuration. Therefore, Stratix V devices do not
Guidelines.
CCIO
9–38.
of the bank is set to 2.5 V or lower, V
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
CCPGM
CCIO
. If V
CCIO
, for all dedicated configuration pins
.
CCIO
is set to 3.0 V, V
CCPD
CCPD
, which must
CCPD
chapter.
“Device
Stratix V
must be
must be
9–3