DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 428

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

2–12
Stratix V Device Handbook Volume 3: Transceivers
Non-Bonded Channel Configurations
In non-bonded configurations, the parallel clock is generated by the clock divider of
individual channels.
configuration driven by the channel PLL of channel 4 configured as a CMU PLL
driving the ×1 clock line. The clock divider block of each channel generates its own
parallel clock by dividing down the serial clock from the ×1 clock line.
Figure 2–10. Three Transmit-Only Channels Configured in Non-Bonded Configuration
Ch5
Ch4
Ch3
Parallel Clock
Serial Clock
Parallel and Serial Clocks
CMU PLL
CMU PLL
CMU PLL
Local Clock Divider
Local Clock Divider
Local Clock Divider
Figure 2–10
Transmitter PCS
Transmitter PCS
Transmitter PCS
Clock Divider
Clock Divider
Clock Divider
shows three transmit-only channels in non-bonded
Parallel and Serial Clock
(Only for the Central Clock Divider)
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Chapter 2: Transceiver Clocking in Stratix V Devices
Transmitter PMA
Transmitter PMA
Transmitter PMA
Serializer
Serializer
Serializer
May 2011 Altera Corporation
Internal Clocking
×1 Clock Lines