DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 157

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 4: Clock Networks and PLLs in Stratix V Devices
Stratix V PLLs
Figure 4–14. clkena Signals
Note to
(1) You can use the clkena signals to enable or disable the GCLK and RCLK networks or the FPLL_<#>_CLKOUT pins.
Stratix V PLLs
May 2011 Altera Corporation
output of the AND gate
with R2 bypassed
output of the AND gate
with R2 not bypassed
Figure
output of
the clock
select mux
clkena
4–14:
In Stratix V devices, the clkena signals are supported at the clock network level
instead of at the PLL output counter level. This allows you to gate off the clock even
when you are not using a PLL. You can also use the clkena signals to control the
dedicated external clocks from the PLLs.
a clock output enable. clkena is synchronous to the falling edge of the clock output.
Stratix V devices also have an additional metastability register that aids in
asynchronous enable and disable of the GCLK and RCLK networks. You can
optionally bypass this register in the Quartus II software.
The PLL can remain locked independent of the clkena signals because the
loop-related counters are not affected. This feature is useful for applications that
require a low-power or sleep mode. The clkena signal can also disable clock outputs if
the system is not tolerant of frequency overshoot during resynchronization.
Stratix V device family introduces the fractional PLLs in addition to the existing
integer PLLs that provide robust clock management and synthesis for device clock
management, external system clock management, and high-speed I/O interfaces.
Each fractional PLL has 18 output counters that supports integer or fractional
frequency synthesis.
Stratix V devices offer up to 28 fractional PLLs in the larger densities. All Stratix V
fractional PLLs have the same core analog structure and features support.
(Note 1)
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Figure 4–14
shows a waveform example for
4–17