DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 149

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DK-DEV-5SGXEA7/ES

Manufacturer Part Number
DK-DEV-5SGXEA7/ES
Description
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer
Altera
Series
Stratix® Vr
Type
FPGAr
Datasheets

Specifications of DK-DEV-5SGXEA7/ES

Contents
Board
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
Stratix® V 5SGXEA7
Other names
544-2725
Table 4–2. Clock Input Pin Connectivity to the GCLK Networks—Preliminary
GCLK0
GCLK1
GCLK2
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
GCLK13
GCLK14
GCLK15
Note to
(1) This is only applicable to 5SGSD6 and 5SGSD8 devices.
Resources
Clock
Table
4–2:
v
v
v
v
0
v
v
v
v
1
Clock Input Pin Connections to GCLK and RCLK Networks
Table 4–2
v
v
v
v
2
v
v
v
v
3
lists the connection between the dedicated clock input pins and GCLKs.
v
v
v
v
4
v
v
v
v
5
v
v
v
v
6
v
v
v
v
7
v
v
v
v
8
v
v
v
v
9
10
v
v
v
v
11
v
v
v
v
12
v
v
v
v
CLK (p/n Pins)
13
v
v
v
v
14
v
v
v
v
15
v
v
v
v
16
v
v
v
v
17
v
v
v
v
18
v
v
v
v
19
v
v
v
v
20
v
v
v
v
21
v
v
v
v
22
v
v
v
v
23
v
v
v
v
24
v
v
v
v
(1)
(1)
(1)
(1)
25
v
(1)
v
(1)
v
(1)
v
(1)
26
v
(1)
v
(1)
v
(1)
v
(1)
27
v
v
v
v
(1)
(1)
(1)
(1)

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