DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 319

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Stratix V Devices
Device Configuration Pins
Table 9–13. Configuration Pin Summary for Stratix V Devices (Part 2 of 2)
Table 9–14. Configuration Pins Description (Part 1 of 3)
May 2011 Altera Corporation
AS_DATA[3..1]
Notes to
(1) This is a dual-purpose pin. This pin is available as an I/O if the associated option that enables this pin is turned off from the Configuration panel
(2) This is a dual-purpose pin. The state of this pin in user mode depends on the Dual-purpose Pins settings in the Device and Pins Option.
(3) This pin is available as an I/O if this pin is not feeding the next device's nCE in a multi-device configuration. To use this pin to feed the next
(4) This pin is powered up by V
(5) Although nIO_PULLUP is powered up by V
TDI
TMS
TCK
TRST
TDO
CLKUSR
in the Device and Pins Option settings. For example, the DEV_OE is available as a user I/O if the Enable device-wide output enable option is
turned off.
device's nCE in a multi-device chain, turn on Enable INIT_DONE output option under Device and Pins Option, General panel in the Quartus II
Software.
I/O in user mode.
pull-down resistor.
(1)
Pin Name
(1)
(1)
(1)
(1)
Table
Description
9–13:
Dedicated test data input. Serial input pin for instructions as well as test and programming data. Data
is shifted on the rising edge of TCK.
This pin has an internal 25-k
Dedicated test mode select. Input pin that provides the control signal to determine the transitions of
the TAP controller state machine. TMS is evaluated on the rising edge of TCK. Therefore, you must set
up TMS before the rising edge of TCK. Transitions in the state machine occur on the falling edge of
TCK after the signal is applied to TMS.
This pin has an internal 25-k
Dedicated test clock input. Clock input to the BST circuitry. Some operations occur at the rising edge,
while others occur at the falling edge. It is expected that the clock input waveform have a nominal 50%
duty cycle.
This pin has an internal 25-k
Dedicated test reset input. Active-low input to asynchronously reset the boundary-scan circuit. The
TRST pin is optional according to the IEEE Std. 1149.1 standard.
Connecting this pin low disables the JTAG circuitry. This pin has an internal 25-k
always active.
Dedicated test data output. Serial data output pin for instructions as well as test and programming
data. Data is shifted out on the falling edge of TCK. This pin is tri-stated if the data is not being shifted
out of the device.
Optional user-supplied clock input. It synchronizes the initialization of one or more devices. Enable
this pin by turning on the Enable user-supplied start-up clock (CLKUSR) option under Device and
Pins Option, Configuration panel in the Quartus II software.
Table 9–14
CCPGM
during configuration. It is powered up by V
Input/Output
Bidirectional
lists the configuration pin descriptions.
CC
, Altera recommends connecting this pin to V



pull-up that is always active.
pull-up that is always active.
pull-down that is always active.
User Mode
—
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
Description
CCIO
of the bank in which the pin resides if it is used as a regular
Powered By
V
CCPGM
CCPGM
or GND directly without using a pull-up or
Configuration Scheme

pull-up that is
AS
9–39