DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 55

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 2: DC and Switching Characteristics for Stratix V Devices
Switching Characteristics
Table 2–31. Memory Output Clock Jitter Specification for Stratix V Devices—Preliminary
May 2011 Altera Corporation
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Notes to
(1) The numbers are preliminary pending silicon characterization.
(2) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(3) The clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by
a PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
Table
Parameter
2–31:
Table 2–30
Table 2–30. DQS Phase Shift Error Specification for DLL-Delayed Clock (t
Devices—Preliminary
Table 2–31
Notes to
(1) The numbers are preliminary pending silicon characterization.
(2) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
Number of DQS Delay
buffers in a –2 speed grade is ±78 ps or ±39 ps.
Regional
Regional
Regional
Network
Global
Global
Global
Table
Clock
Buffers
lists the DQS phase shift error for Stratix V devices.
lists the memory output clock jitter specifications for Stratix V devices.
1
2
3
4
2–30:
Symbol
t
t
t
t
t
JIT(duty)
t
JIT(duty)
JIT(per)
JIT(per)
JIT(cc)
JIT(cc)
(Note
1),
–2 Speed Grade
–2 Speed Grade
-100
-150
Min
-50
-50
-75
-75
(2)
104
26
52
78
Max
100
150
50
50
75
75
Stratix V Device Handbook Volume 1: Overview and Datasheet
–3 Speed Grade
–3 Speed Grade
-82.5
-82.5
-110
-165
Min
-55
-90
112
28
56
84
Max
82.5
82.5
110
165
55
90
(Note 1)
–4 Speed Grade
–4 Speed Grade
-82.5
-82.5
-110
-165
Min
-55
-90
DQS_PSERR
120
30
60
90
,
(2),
) for Stratix V
Max
82.5
82.5
(3)
110
165
55
90
Unit
ps
ps
ps
ps
Unit
ps
ps
ps
ps
ps
ps
2–27