DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 266

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

7–22
Figure 7–12. IOE Input Registers for Stratix V Devices
Notes to
(1) You can bypass the register or read FIFO block in this path.
(2) The input clock can be from the DQS logic block or from a global clock line.
(3) This input clock comes from the CQn logic block.
(4) This half rate-read clock comes from a PLL through the clock network.
(5) The DQS and DQSn signals must be inverted for DDR3 and DDR2 SDRAM interfaces. When using Altera’s memory interface IPs, the DQS and
Stratix V Device Handbook Volume 2: Device Interfaces and Integration
DQSn signals are automatically inverted.
DQS/CQ (2), (5)
Figure
I/O Element Registers
DQSn (5)
7–12:
CQn (3)
f
For more information about dynamic OCT control, refer to the
Devices
The IOE registers are expanded to allow source-synchronous systems to have faster
register-to-register transfers and resynchronization. Both top, bottom, and right IOEs
have the same capability.
Figure 7–12
consists of the DDR input registers and the read FIFO block. You can bypass each
block of the input path.
There are three registers in the DDR input registers block. Two registers capture data
on the positive and negative edges of the clock while the third register aligns the
captured data. You can choose to use the same clock for the positive and negative
edge registers or two complementary clocks (DQS/CQ for the positive-edge register
and DQSn/CQn for the negative-edge register). The third register that aligns the
captured data uses the same clock as the positive edge registers.
The read FIFO block resynchronizes the data to the system clock domain, as well as to
lower the data rate to half rate.
For more information about the read-leveling delay chain, refer to
Circuitry” on page
Figure 7–13
paths. The path is divided into the HDR block, alignment registers, and output and
output-enable registers. The device can bypass each block of the output and
output-enable path.
Differential
Input
Buffer
DQ
chapter.
0
1
shows the registers available in the Stratix V input path. The input path
shows the registers available in the Stratix V output and output-enable
Double Data Rate Input Registers
Input Reg A
Input Reg B
D
D
D
DFF
DFF
7–20.
Q
Q
Q
I
I
neg_reg_out
(Note 1)
Input Reg C
D
DFF
Q
I
Chapter 7: External Memory Interfaces in Stratix V Devices
datain [1]
datain [0]
wrclk
Read FIFO
dataout[3..0]
Stratix V External Memory Interface Features
rdclk
I/O Features in Stratix V
May 2011 Altera Corporation
“Leveling
To core
Half-rate (4)
clock