DK-DEV-5SGXEA7/ES Altera, DK-DEV-5SGXEA7/ES Datasheet - Page 401

• Manufacturer Part Number: DK-DEV-5SGXEA7/ES
• Description: KIT DEV STRATIX V FPGA 5SGXEA7
• Manufacturer: Altera
• Series: Stratix® Vr
• Type: FPGAr

Specifications of DK-DEV-5SGXEA7/ES

• Contents: Board
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: Stratix® V 5SGXEA7
• Other names: 544-2725

Chapter 1: Transceiver Architecture in Stratix V Devices
Standard PCS Architecture
May 2011 Altera Corporation
Transmitter Standard PCS Datapath
1
The transmitter PCS datapath, shown in
following blocks:
■
■
■
Transmitter Phase Compensation FIFO
The transmitter phase compensation FIFO interfaces with the transmitter channel PCS
and the FPGA fabric or PCIe interface. It compensates for the phase difference
between the low-speed parallel clock and the FPGA fabric interface clock.
shows the datapath and clocking of the transmitter phase compensation FIFO.
Figure 1–24. Transmitter Phase Compensation FIFO
Byte Serializer
The byte serializer divides the input datapath by two. This allows you to run the
transceiver channel at higher data rates while keeping the FPGA fabric interface
frequency within the maximum limit. In single-width mode, it converts the two-byte
wide datapath to a one-byte wide datapath. In double-width mode, it converts the
four-byte wide datapath to a two-byte wide datapath. It is optional in configurations
that do not exceed the FPGA fabric-transceiver interface maximum frequency limit.
The byte deserializer is required in configurations that exceed the FPGA
fabric-transceiver interface maximum frequency limit.
“Transmitter Phase Compensation FIFO” on page 1–29
“Byte Serializer” on page 1–29
“8B/10B Encoder” on page 1–30
Datapath from the FPGA
Fabric or PIPE Interface
tx_coreclk
wr_clk
Compensation
(only available in PCIe configurations)
Phase
FIFO
TX
Figure 1–16 on page
rd_clk
Stratix V Device Handbook Volume 3: Transceivers
or the 8B/10B Encoder or Serializer
Datapath to the Byte Serializer
tx_clkout
coreclkout
1–18, consists of the
Figure 1–24
1–29